# HG changeset patch # User Dmitriy Taychenachev # Date 1248867369 -32400 diff --git a/arch/arm/Makefile b/arch/arm/Makefile --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -158,6 +158,7 @@ machine-$(CONFIG_ARCH_VERSATILE) := versatile machine-$(CONFIG_ARCH_W90X900) := w90x900 machine-$(CONFIG_FOOTBRIDGE) := footbridge +machine-$(CONFIG_ARCH_SCMA11) := scma11 # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. diff --git a/arch/arm/mach-scma11/Kconfig b/arch/arm/mach-scma11/Kconfig new file mode 100644 --- /dev/null +++ b/arch/arm/mach-scma11/Kconfig @@ -0,0 +1,11 @@ +config MACH_MAGX_E8 + bool "Support Motorola E8 GSM phone" + default n + help + Include support for Motorola E8 phone. + +config MACH_MAGX_ZN5 + bool "Support Motorola Zn5 GSM phone" + default n + help + Include support for Motorola Zn5 GSM phone. diff --git a/arch/arm/mach-scma11/Makefile b/arch/arm/mach-scma11/Makefile new file mode 100644 --- /dev/null +++ b/arch/arm/mach-scma11/Makefile @@ -0,0 +1,3 @@ +obj-y := mm.o clock.o devices.o iomux.o scma11phone.o +obj-$(CONFIG_MACH_MAGX_E8) += magx-e8.o +obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o diff --git a/arch/arm/mach-scma11/Makefile.boot b/arch/arm/mach-scma11/Makefile.boot new file mode 100644 --- /dev/null +++ b/arch/arm/mach-scma11/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x90008000 +params_phys-y := 0x90000100 +initrd_phys-y := 0x90800000 diff --git a/arch/arm/mach-scma11/clock.c b/arch/arm/mach-scma11/clock.c new file mode 100644 --- /dev/null +++ b/arch/arm/mach-scma11/clock.c @@ -0,0 +1,650 @@ +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "crm_regs.h" + +#define CRM_SMALL_DIVIDER(base, name) \ + __crm_small_divider(base, \ + base ## _ ## name ## _OFFSET, \ + base ## _ ## name ## _MASK) +#define CRM_1DIVIDER(base, name) \ + __crm_divider(base, \ + base ## _ ## name ## _OFFSET,\ + base ## _ ## name ## _MASK, 1) +#define CRM_16DIVIDER(base, name) \ + __crm_divider(base, \ + base ## _ ## name ## _OFFSET, \ + base ## _ ## name ## _MASK, 16) + +static u32 __crm_small_divider(void __iomem *reg, u8 offset, u32 mask) +{ + static const u32 crm_small_dividers[] = { + 2, 3, 4, 5, 6, 8, 10, 12 + }; + u8 idx; + + idx = (__raw_readl(reg) & mask) >> offset; + if (idx > 7) + return 1; + + return crm_small_dividers[idx]; +} + +static u32 __crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z) +{ + u32 div; + div = (__raw_readl(reg) & mask) >> offset; + return div ? div : z; +} + +static int _clk_1bit_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void _clk_1bit_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(1 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static int _clk_3bit_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg |= 0x7 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void _clk_3bit_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(0x7 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static unsigned long ckih_rate; + +static unsigned long _clk_ckih_get_rate(struct clk *clk) +{ + return ckih_rate; +} + +static struct clk ckih_clk = { + .get_rate = _clk_ckih_get_rate, +}; + +static unsigned long _clk_ckih_x2_get_rate(struct clk *clk) +{ + return 2 * clk_get_rate(clk->parent); +} + +static struct clk ckih_x2_clk = { + .parent = &ckih_clk, + .get_rate = _clk_ckih_x2_get_rate, +}; + +static unsigned long _clk_ckil_get_rate(struct clk *clk) +{ + return CKIL_CLK_FREQ; +} + +static struct clk ckil_clk = { + .get_rate = _clk_ckil_get_rate, +}; + +/* plls stuff */ +static struct clk mcu_pll_clk; +static struct clk dsp_pll_clk; +static struct clk usb_pll_clk; + +static struct clk *__pll_clk(u8 sel) +{ + switch (sel) { + case 0: + return &mcu_pll_clk; + case 1: + return &dsp_pll_clk; + case 2: + return &usb_pll_clk; + } + BUG(); +} + +static u8 __pll_num(struct clk *clk) +{ + if (clk == &mcu_pll_clk) + return 0; + else if (clk == &dsp_pll_clk) + return 1; + else if (clk == &usb_pll_clk) + return 2; + BUG(); +} + +static void __iomem *__pll_base(struct clk *clk) +{ + static void __iomem *plls[] = { + IO_ADDRESS(PLL0_BASE_ADDR), + IO_ADDRESS(PLL1_BASE_ADDR), + IO_ADDRESS(PLL2_BASE_ADDR), + }; + return plls[__pll_num(clk)]; +} + +static unsigned long _clk_pll_get_rate(struct clk *clk) +{ + const void __iomem *pllbase; + unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi; + long mfn, mfn_abs, mfd, pdf; + s64 temp; + pllbase = __pll_base(clk); + + pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM; + if (pll_hfsm == 0) { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); + } else { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); + } + + pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; + mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK; + mfi = (mfi <= 5) ? 5 : mfi; + mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; + mfn = dp_mfn & MXC_PLL_DP_MFN_MASK; + mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000); + + if (mfn < 0) + mfn_abs = -mfn; + else + mfn_abs = mfn; + +/* XXX: actually this asumes that ckih is fed to pll, but spec says + * that ckih_x2 is also possible. need to check this out. + */ + ref_clk = clk_get_rate(&ckih_clk); + + ref_clk *= 2; + ref_clk /= pdf + 1; + + temp = (u64) ref_clk * mfn_abs; + do_div(temp, mfd); + if (mfn < 0) + temp = -temp; + temp += ref_clk * mfi; + + return temp; +} + +static int _clk_pll_enable(struct clk *clk) +{ + void __iomem *ctl; + u32 reg; + + ctl = __pll_base(clk); + reg = __raw_readl(ctl); + reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN); + __raw_writel(reg, ctl); + do { + reg = __raw_readl(ctl); + } while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF); + return 0; +} + +static void _clk_pll_disable(struct clk *clk) +{ + void __iomem *ctl; + u32 reg; + + ctl = __pll_base(clk); + reg = __raw_readl(ctl); + reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN); + __raw_writel(reg, ctl); +} + +static struct clk mcu_pll_clk = { + .parent = &ckih_clk, + .get_rate = _clk_pll_get_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +static struct clk dsp_pll_clk = { + .parent = &ckih_clk, + .get_rate = _clk_pll_get_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +static struct clk usb_pll_clk = { + .parent = &ckih_clk, + .get_rate = _clk_pll_get_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; +/* plls stuff end */ + +/* ap_ref_clk stuff */ +static struct clk ap_ref_clk; + +static unsigned long _clk_ap_ref_get_rate(struct clk *clk) +{ + u32 ascsr, acsr; + u8 ap_pat_ref_div_2, ap_isel, acs, ads; + + ascsr = __raw_readl(MXC_CRMAP_ASCSR); + acsr = __raw_readl(MXC_CRMAP_ACSR); + + /* 0 for ckih, 1 for ckih*2 */ + ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL; + /* reg divider */ + ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1; + /* undocumented, 1 for disabling divider */ + ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1; + /* 0 for pat_ref, 1 for divider out */ + acs = acsr & MXC_CRMAP_ACSR_ACS; + + if (acs & !ads) + /* use divided clock */ + return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1); + + return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1); +} + +static struct clk ap_ref_clk = { + .parent = &ckih_clk, + .get_rate = _clk_ap_ref_get_rate, +}; +/* ap_ref_clk stuff end */ + +/* ap_pre_dfs_clk stuff */ +static struct clk ap_pre_dfs_clk; + +static unsigned long _clk_ap_pre_dfs_get_rate(struct clk *clk) +{ + u32 acsr, ascsr; + + acsr = __raw_readl(MXC_CRMAP_ACSR); + ascsr = __raw_readl(MXC_CRMAP_ASCSR); + + if (acsr & MXC_CRMAP_ACSR_ACS) { + u8 sel; + sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >> + MXC_CRMAP_ASCSR_APSEL_OFFSET; + return clk_get_rate(__pll_clk(sel)) / + CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV); + } + return clk_get_rate(&ap_ref_clk); +} + +static struct clk ap_pre_dfs_clk = { + .get_rate = _clk_ap_pre_dfs_get_rate, +}; +/* ap_pre_dfs_clk stuff end */ + +/* usb_clk stuff */ +static struct clk usb_clk; + +static struct clk *__clk_usb_parent(struct clk *clk) +{ + u32 acsr, ascsr; + + acsr = __raw_readl(MXC_CRMAP_ACSR); + ascsr = __raw_readl(MXC_CRMAP_ASCSR); + + if (acsr & MXC_CRMAP_ACSR_ACS) { + u8 sel; + sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >> + MXC_CRMAP_ASCSR_USBSEL_OFFSET; + return __pll_clk(sel); + } + return &ap_ref_clk; +} + +static unsigned long _clk_usb_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / + CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV); +} + +static struct clk usb_clk = { + .enable_reg = MXC_CRMAP_ACDER2, + .enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET, + .get_rate = _clk_usb_get_rate, + .enable = _clk_1bit_enable, + .disable = _clk_1bit_disable, +}; +/* usb_clk stuff end */ + +static unsigned long _clk_ipg_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV); +} + +static unsigned long _clk_ahb_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / + CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV); +} + +static struct clk ipg_clk = { + .parent = &ap_pre_dfs_clk, + .get_rate = _clk_ipg_get_rate, +}; + +static struct clk ahb_clk = { + .parent = &ap_pre_dfs_clk, + .get_rate = _clk_ahb_get_rate, +}; + +/* perclk_clk stuff */ +static struct clk perclk_clk; + +static unsigned long _clk_perclk_get_rate(struct clk *clk) +{ + u32 acder2; + + acder2 = __raw_readl(MXC_CRMAP_ACDER2); + if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK) + return 2 * clk_get_rate(clk->parent); + + return clk_get_rate(clk->parent); +} + +static struct clk perclk_clk = { + .parent = &ckih_clk, + .get_rate = _clk_perclk_get_rate, +}; +/* perclk_clk stuff end */ + +/* uart_clk stuff */ +static struct clk uart_clk[]; + +static unsigned long _clk_uart_get_rate(struct clk *clk) +{ + u32 div; + + switch (clk->id) { + case 0: + case 1: + div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV); + break; + case 2: + div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV); + break; + default: + BUG(); + } + return clk_get_rate(clk->parent) / div; +} + +static struct clk uart_clk[] = { + { + .id = 0, + .parent = &perclk_clk, + .enable_reg = MXC_CRMAP_APRA, + .enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET, + .get_rate = _clk_uart_get_rate, + .enable = _clk_1bit_enable, + .disable = _clk_1bit_disable, + }, { + .id = 1, + .parent = &perclk_clk, + .enable_reg = MXC_CRMAP_APRA, + .enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET, + .get_rate = _clk_uart_get_rate, + .enable = _clk_1bit_enable, + .disable = _clk_1bit_disable, + }, { + .id = 2, + .parent = &perclk_clk, + .enable_reg = MXC_CRMAP_APRA, + .enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET, + .get_rate = _clk_uart_get_rate, + .enable = _clk_1bit_enable, + .disable = _clk_1bit_disable, + }, +}; +/* uart_clk stuff end */ + +/* sdhc_clk stuff */ +static struct clk nfc_clk; + +static unsigned long _clk_nfc_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / + CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV); +} + +static struct clk nfc_clk = { + .parent = &ahb_clk, + .enable_reg = MXC_CRMAP_ACDER2, + .enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET, + .get_rate = _clk_nfc_get_rate, + .enable = _clk_1bit_enable, + .disable = _clk_1bit_disable, +}; +/* sdhc_clk stuff end */ + +/* sdhc_clk stuff */ +static struct clk sdhc_clk[]; + +static struct clk *__clk_sdhc_parent(struct clk *clk) +{ + u32 aprb; + u8 sel; + u32 mask; + int offset; + + aprb = __raw_readl(MXC_CRMAP_APRB); + + switch (clk->id) { + case 0: + mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK; + offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET; + break; + case 1: + mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK; + offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET; + break; + default: + BUG(); + } + sel = (aprb & mask) >> offset; + + switch (sel) { + case 0: + return &ckih_clk; + case 1: + return &ckih_x2_clk; + } + return &usb_clk; +} + +static unsigned long _clk_sdhc_get_rate(struct clk *clk) +{ + u32 div; + + switch (clk->id) { + case 0: + div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV); + break; + case 1: + div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV); + break; + default: + BUG(); + } + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_sdhc_enable(struct clk *clk) +{ + u32 amlpmre1, aprb; + + amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1); + aprb = __raw_readl(MXC_CRMAP_APRB); + switch (clk->id) { + case 0: + amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET); + aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET); + break; + case 1: + amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET); + aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET); + break; + } + __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1); + __raw_writel(aprb, MXC_CRMAP_APRB); + return 0; +} + +static void _clk_sdhc_disable(struct clk *clk) +{ + u32 amlpmre1, aprb; + + amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1); + aprb = __raw_readl(MXC_CRMAP_APRB); + switch (clk->id) { + case 0: + amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET); + aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET); + break; + case 1: + amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET); + aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET); + break; + } + __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1); + __raw_writel(aprb, MXC_CRMAP_APRB); +} + +static struct clk sdhc_clk[] = { + { + .id = 0, + .get_rate = _clk_sdhc_get_rate, + .enable = _clk_sdhc_enable, + .disable = _clk_sdhc_disable, + }, { + .id = 1, + .get_rate = _clk_sdhc_get_rate, + .enable = _clk_sdhc_enable, + .disable = _clk_sdhc_disable, + }, +}; +/* sdhc_clk stuff end */ + +/* wdog_clk stuff */ +static struct clk wdog_clk[] = { + { + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CRMAP_AMLPMRD, + .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET, + .enable = _clk_3bit_enable, + .disable = _clk_3bit_disable, + }, { + .id = 1, + .parent = &ipg_clk, + .enable_reg = MXC_CRMAP_AMLPMRD, + .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET, + .enable = _clk_3bit_enable, + .disable = _clk_3bit_disable, + }, +}; +/* wdog_clk stuff end */ + +/* gpt_clk stuff */ +static struct clk gpt_clk = { + .parent = &ipg_clk, + .enable_reg = MXC_CRMAP_AMLPMRC, + .enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET, + .enable = _clk_3bit_enable, + .disable = _clk_3bit_disable, +}; +/* gpt_clk stuff end */ + +/* cspi_clk stuff */ +static struct clk cspi_clk[] = { + { + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CRMAP_AMLPMRE2, + .enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET, + .enable = _clk_3bit_enable, + .disable = _clk_3bit_disable, + }, { + .id = 1, + .parent = &ipg_clk, + .enable_reg = MXC_CRMAP_AMLPMRE1, + .enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET, + .enable = _clk_3bit_enable, + .disable = _clk_3bit_disable, + }, +}; +/* cspi_clk stuff end */ + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = d, \ + .con_id = n, \ + .clk = &c, \ + }, + +static struct clk_lookup lookups[] = { + _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]) + _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1]) + _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[3]) + _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0]) + _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1]) + _REGISTER_CLOCK("scma11-wdt.0", NULL, wdog_clk[0]) + _REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0]) + _REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1]) +}; + +int __init scma11_clocks_init(unsigned long fref) +{ + int i; + + ckih_rate = fref; + + usb_clk.parent = __clk_usb_parent(&usb_clk); + sdhc_clk[0].parent = __clk_sdhc_parent(&sdhc_clk[0]); + sdhc_clk[1].parent = __clk_sdhc_parent(&sdhc_clk[1]); + + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); + + mxc_timer_init(&gpt_clk); + + return 0; +} diff --git a/arch/arm/mach-scma11/crm_regs.h b/arch/arm/mach-scma11/crm_regs.h new file mode 100644 --- /dev/null +++ b/arch/arm/mach-scma11/crm_regs.h @@ -0,0 +1,418 @@ +/* + * Copyright 2006 Freescale Semiconductor, Inc. + * Copyright 2006-2007 Motorola, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* Date Author Comment + * =========== ============== ============================================== + * 06-Oct-2006 Motorola Support for power management + * 20-Oct-2006 Motorola Added offset and mask for IPU PAD settings. + * 05-Dec-2006 Motorola Moved PLL defines from mxc_pm.c + * 09-Jan-2007 Motorola Implement MGPER fix for crash after WFI. + * 12-Jan-2007 Motorola Set clkctl_gp_ctrl[7] to enable JTAG debugging. + * 16-Jan-2007 Motorola Add DSM CONTROL1 definitions. + */ + +#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ +#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ + +#define CKIL_CLK_FREQ 32768 + +#define MXC_CRM_AP_BASE (IO_ADDRESS(CRM_AP_BASE_ADDR)) + +#define MXC_CRM_COM_BASE (IO_ADDRESS(CRM_COM_BASE_ADDR)) + +#define MXC_DSM_BASE (IO_ADDRESS(DSM_BASE_ADDR)) + +#define MXC_PLL0_BASE (IO_ADDRESS(PLL0_BASE_ADDR)) + +#define MXC_PLL1_BASE (IO_ADDRESS(PLL1_BASE_ADDR)) + +#define MXC_PLL2_BASE (IO_ADDRESS(PLL2_BASE_ADDR)) + +/* PLL Register Offsets */ +#define MXC_PLL_DP_CTL 0x00 +#define MXC_PLL_DP_CONFIG 0x04 +#define MXC_PLL_DP_OP 0x08 +#define MXC_PLL_DP_MFD 0x0C +#define MXC_PLL_DP_MFN 0x10 +#define MXC_PLL_DP_HFS_OP 0x1C +#define MXC_PLL_DP_HFS_MFD 0x20 +#define MXC_PLL_DP_HFS_MFN 0x24 + +/* PLL Register Bit definitions */ +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 +#define MXC_PLL_DP_CTL_ADE 0x800 +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 +#define MXC_PLL_DP_CTL_HFSM 0x80 +#define MXC_PLL_DP_CTL_PRE 0x40 +#define MXC_PLL_DP_CTL_UPEN 0x20 +#define MXC_PLL_DP_CTL_RST 0x10 +#define MXC_PLL_DP_CTL_RCP 0x8 +#define MXC_PLL_DP_CTL_PLM 0x4 +#define MXC_PLL_DP_CTL_BRM0 0x2 +#define MXC_PLL_DP_CTL_LRF 0x1 + +#define MXC_PLL_DP_OP_MFI_OFFSET 4 +#define MXC_PLL_DP_OP_MFI_MASK 0xF +#define MXC_PLL_DP_OP_PDF_OFFSET 0 +#define MXC_PLL_DP_OP_PDF_MASK 0xF + +#define MXC_PLL_DP_MFD_OFFSET 0 +#define MXC_PLL_DP_MFD_MASK 0x7FFFFFF + +#define MXC_PLL_DP_MFN_OFFSET 0 +#define MXC_PLL_DP_MFN_MASK 0x7FFFFFF + +/* CRM AP Register Offsets */ +#define MXC_CRMAP_ASCSR IO_ADDRESS(CRM_AP_BASE_ADDR + 0x00) +#define MXC_CRMAP_ACDR IO_ADDRESS(CRM_AP_BASE_ADDR + 0x04) +#define MXC_CRMAP_ACDER1 IO_ADDRESS(CRM_AP_BASE_ADDR + 0x08) +#define MXC_CRMAP_ACDER2 IO_ADDRESS(CRM_AP_BASE_ADDR + 0x0C) +#define MXC_CRMAP_ACGCR IO_ADDRESS(CRM_AP_BASE_ADDR + 0x10) +#define MXC_CRMAP_ACCGCR IO_ADDRESS(CRM_AP_BASE_ADDR + 0x14) +#define MXC_CRMAP_AMLPMRA IO_ADDRESS(CRM_AP_BASE_ADDR + 0x18) +#define MXC_CRMAP_AMLPMRB IO_ADDRESS(CRM_AP_BASE_ADDR + 0x1C) +#define MXC_CRMAP_AMLPMRC IO_ADDRESS(CRM_AP_BASE_ADDR + 0x20) +#define MXC_CRMAP_AMLPMRD IO_ADDRESS(CRM_AP_BASE_ADDR + 0x24) +#define MXC_CRMAP_AMLPMRE1 IO_ADDRESS(CRM_AP_BASE_ADDR + 0x28) +#define MXC_CRMAP_AMLPMRE2 IO_ADDRESS(CRM_AP_BASE_ADDR + 0x2C) +#define MXC_CRMAP_AMLPMRF IO_ADDRESS(CRM_AP_BASE_ADDR + 0x30) +#define MXC_CRMAP_AMLPMRG IO_ADDRESS(CRM_AP_BASE_ADDR + 0x34) +#define MXC_CRMAP_APGCR IO_ADDRESS(CRM_AP_BASE_ADDR + 0x38) +#define MXC_CRMAP_ACSR IO_ADDRESS(CRM_AP_BASE_ADDR + 0x3C) +#define MXC_CRMAP_ADCR IO_ADDRESS(CRM_AP_BASE_ADDR + 0x40) +#define MXC_CRMAP_ACR IO_ADDRESS(CRM_AP_BASE_ADDR + 0x44) +#define MXC_CRMAP_AMCR IO_ADDRESS(CRM_AP_BASE_ADDR + 0x48) +#define MXC_CRMAP_APCR IO_ADDRESS(CRM_AP_BASE_ADDR + 0x4C) +#define MXC_CRMAP_AMORA IO_ADDRESS(CRM_AP_BASE_ADDR + 0x50) +#define MXC_CRMAP_AMORB IO_ADDRESS(CRM_AP_BASE_ADDR + 0x54) +#define MXC_CRMAP_AGPR IO_ADDRESS(CRM_AP_BASE_ADDR + 0x58) +#define MXC_CRMAP_APRA IO_ADDRESS(CRM_AP_BASE_ADDR + 0x5C) +#define MXC_CRMAP_APRB IO_ADDRESS(CRM_AP_BASE_ADDR + 0x60) +#define MXC_CRMAP_APOR IO_ADDRESS(CRM_AP_BASE_ADDR + 0x64) +#define MXC_CRMAP_ADFMR IO_ADDRESS(CRM_AP_BASE_ADDR + 0x68) + +/* CRM AP Register Bit definitions */ +#define MXC_CRMAP_ASCSR_CRS 0x10000 +#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET 15 +#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2 0x8000 +#define MXC_CRMAP_ASCSR_USBSEL_OFFSET 13 +#define MXC_CRMAP_ASCSR_USBSEL_MASK (0x3 << 13) +#define MXC_CRMAP_ASCSR_CSISEL_OFFSET 11 +#define MXC_CRMAP_ASCSR_CSISEL_MASK (0x3 << 11) +#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET 7 +#define MXC_CRMAP_ASCSR_SSI2SEL_MASK (0x3 << 7) +#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET 5 +#define MXC_CRMAP_ASCSR_SSI1SEL_MASK (0x3 << 5) +#define MXC_CRMAP_ASCSR_APSEL_OFFSET 3 +#define MXC_CRMAP_ASCSR_APSEL_MASK (0x3 << 3) +#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET 2 +#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1 0x4 +#define MXC_CRMAP_ASCSR_APISEL 0x1 + +#define MXC_CRMAP_ACDR_ARMDIV_OFFSET 8 +#define MXC_CRMAP_ACDR_ARMDIV_MASK (0xF << 8) +#define MXC_CRMAP_ACDR_AHBDIV_OFFSET 4 +#define MXC_CRMAP_ACDR_AHBDIV_MASK (0xF << 4) +#define MXC_CRMAP_ACDR_IPDIV_OFFSET 0 +#define MXC_CRMAP_ACDR_IPDIV_MASK 0xF + +#define MXC_CRMAP_ACDER1_CSIEN 0x40000000 +#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET 24 +#define MXC_CRMAP_ACDER1_CSIDIV_MASK (0x3F << 24) +#define MXC_CRMAP_ACDER1_SSI2EN 0x4000 +#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET 8 +#define MXC_CRMAP_ACDER1_SSI2DIV_MASK (0x3F << 8) +#define MXC_CRMAP_ACDER1_SSI1EN 0x40 +#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET 0 +#define MXC_CRMAP_ACDER1_SSI1DIV_MASK 0x3F + +#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFF 24 +#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MSK (0x7 << 24) +#define MXC_CRMAP_ACDER2_NFCEN_OFFSET 20 +#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET 16 +#define MXC_CRMAP_ACDER2_NFCDIV_MASK (0xF << 16) +#define MXC_CRMAP_ACDER2_USBEN_OFFSET 12 +#define MXC_CRMAP_ACDER2_USBDIV_OFFSET 8 +#define MXC_CRMAP_ACDER2_USBDIV_MASK (0xF << 8) +#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFF 5 +#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK (0x3 << 5) +#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET 0 +#define MXC_CRMAP_ACDER2_BAUDDIV_MASK 0xF + +#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET 22 +#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK (0x7 << 22) +#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET 19 +#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK (0x7 << 19) +#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET 12 +#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK (0x7 << 12) +#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET 9 +#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK (0x7 << 9) +#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET 6 +#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK (0x7 << 6) +#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET 3 +#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK (0x7 << 3) + +#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET 0 +#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK 0x7 + +#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET 28 +#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK (0x7 << 28) +#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET 22 +#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK (0x7 << 22) +#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET 16 +#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK (0x7 << 16) +#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET 12 +#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK (0x7 << 12) +#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET 9 +#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK (0x7 << 9) +#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET 6 +#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK (0x7 << 6) +#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET 3 +#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK (0x7 << 3) +#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET 0 +#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK 0x7 + +#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET 22 +#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK (0x7 << 22) +#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET 12 +#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK (0x7 << 12) +#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET 9 +#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK (0x7 << 9) +#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET 6 +#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK (0x7 << 6) +#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET 0 +#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK 0x7 + +#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET 28 +#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK (0x7 << 28) +#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET 25 +#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK (0x7 << 25) +#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET 22 +#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK (0x7 << 22) +#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET 19 +#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK (0x7 << 19) +#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET 16 +#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK (0x7 << 16) +#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET 12 +#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK (0x7 << 12) +#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET 9 +#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK (0x7 << 9) +#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET 6 +#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK (0x7 << 6) +#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET 3 +#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK (0x7 << 3) +#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET 0 +#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK 0x7 + +#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET 0 +#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK 0x7 + +#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET 19 +#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK (0x7 << 19) +#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET 16 +#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK (0x7 << 16) +#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET 9 +#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK (0x7 << 9) +#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET 6 +#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK (0x7 << 6) +#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET 3 +#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK (0x7 << 3) +#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET 0 +#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK (0x7 << 0) + +#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET 28 +#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK (0x7 << 28) +#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET 22 +#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK (0x7 << 22) +#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET 19 +#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK (0x7 << 19) +#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET 16 +#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK (0x7 << 16) +#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET 12 +#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK (0x7 << 12) +#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET 9 +#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK (0x7 << 9) +#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET 6 +#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK (0x7 << 6) +#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET 3 +#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK (0x7 << 3) +#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET 0 +#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK 0x7 + +#define MXC_CRMAP_AGPR_IPUPAD_OFFSET 20 +#define MXC_CRMAP_AGPR_IPUPAD_MASK (0x7 << 20) + +#define MXC_CRMAP_APRA_UART1EN_OFFSET 0 +#define MXC_CRMAP_APRA_UART2EN_OFFSET 8 +#define MXC_CRMAP_APRA_SAHARA_DIV2_CLK_EN 0x4000 +#define MXC_CRMAP_APRA_MQSPI_EN 0x2000 +#define MXC_CRMAP_APRA_UART3EN_OFFSET 16 +#define MXC_CRMAP_APRA_SIMEN_OFFSET 24 +#define MXC_CRMAP_APRA_UART3DIV_OFFSET 17 +#define MXC_CRMAP_APRA_UART3DIV_MASK (0xF << 17) +#define MXC_CRMAP_APRA_EL1T_EN 0x20000000 + +#define MXC_CRMAP_APRB_SDHC1EN_OFFSET 0 +#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET 1 +#define MXC_CRMAP_APRB_SDHC1_DIV_MASK (0xF << 1) +#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET 5 +#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK (0x7 << 5) +#define MXC_CRMAP_APRB_SDHC2EN_OFFSET 8 +#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET 9 +#define MXC_CRMAP_APRB_SDHC2_DIV_MASK (0xF << 9) +#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET 13 +#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK (0x7 << 13) + +#define MXC_CRMAP_ACSR_ADS_OFFSET 8 +#define MXC_CRMAP_ACSR_ADS (0x1 << 8) +#define MXC_CRMAP_ACSR_ACS 0x1 + +#define MXC_CRMAP_ADCR_LFDF_0 (0x0 << 8) +#define MXC_CRMAP_ADCR_LFDF_2 (0x1 << 8) +#define MXC_CRMAP_ADCR_LFDF_4 (0x2 << 8) +#define MXC_CRMAP_ADCR_LFDF_8 (0x3 << 8) +#define MXC_CRMAP_ADCR_LFDF_OFFSET 8 +#define MXC_CRMAP_ADCR_LFDF_MASK (0x3 << 8) +#define MXC_CRMAP_ADCR_ALT_PLL 0x80 +#define MXC_CRMAP_ADCR_DFS_DIVEN 0x20 +#define MXC_CRMAP_ADCR_DIV_BYP 0x2 +#define MXC_CRMAP_ADCR_VSTAT 0x8 +#define MXC_CRMAP_ADCR_TSTAT 0x10 +#define MXC_CRMAP_ADCR_DVFS_VCTRL 0x10 +#define MXC_CRMAP_ADCR_CLK_ON 0x40 + +#define MXC_CRMAP_ADFMR_FC_OFFSET 16 +#define MXC_CRMAP_ADFMR_FC_MASK (0x1F << 16) +#define MXC_CRMAP_ADFMR_MF_OFFSET 1 +#define MXC_CRMAP_ADFMR_MF_MASK (0x3FF << 1) +#define MXC_CRMAP_ADFMR_DFM_CLK_READY 0x1 +#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN 0x8000 + +#define MXC_CRMAP_ACR_CKOHS_HIGH (1 << 18) +#define MXC_CRMAP_ACR_CKOS_HIGH (1 << 16) +#define MXC_CRMAP_ACR_CKOHS_MASK (0x7 << 12) +#define MXC_CRMAP_ACR_CKOHDIV_MASK (0xF << 8) +#define MXC_CRMAP_ACR_CKOHDIV_OFFSET 8 +#define MXC_CRMAP_ACR_CKOHD (1 << 11) +#define MXC_CRMAP_ACR_CKOS_MASK (0x7 << 4) +#define MXC_CRMAP_ACR_CKOD (1 << 7) + +/* CRM COM Register Offsets */ +#define MXC_CRMCOM_CSCR (MXC_CRM_COM_BASE + 0x0C) +#define MXC_CRMCOM_CCCR (MXC_CRM_COM_BASE + 0x10) + +/* CRM COM Bit Definitions */ +#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET 8 +#define MXC_CRMCOM_CCCR_CC_DIV_MASK (0x1F << 8) +#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET 0 +#define MXC_CRMCOM_CCCR_CC_SEL_MASK 0x3 +#define MXC_CRMCOM_CSCR_CKOHSEL (1 << 18) +#define MXC_CRMCOM_CSCR_CKOSEL (1 << 17) + +/* DSM Register Offsets */ +#define MXC_DSM_CRM_CONTROL (MXC_DSM_BASE + 0x50) +#define MXC_DSM_CONTROL1 (MXC_DSM_BASE + 0x24) +#define MXC_DSM_CONTROL0 (MXC_DSM_BASE + 0x20) +#define MXC_DSM_SLEEP_TIME (MXC_DSM_BASE + 0x0c) +#define MXC_DSM_WARM_PER (MXC_DSM_BASE + 0x40) +#define MXC_DSM_LOCK_PER (MXC_DSM_BASE + 0x44) +#define MXC_DSM_CTREN (MXC_DSM_BASE + 0x28) +#define MXC_DSM_MGPER (MXC_DSM_BASE + 0x4c) + +/* + * Bit definitions of various registers in DSM + */ +#define MXC_DSM_CRM_CTRL_DVFS_BYP 0x00000008 +#define MXC_DSM_CRM_CTRL_DVFS_VCTRL 0x00000004 +#define MXC_DSM_CRM_CTRL_LPMD1 0x00000002 +#define MXC_DSM_CRM_CTRL_LPMD0 0x00000001 +#define MXC_DSM_CONTROL0_STBY_COMMIT_EN 0x00000200 +#define MXC_DSM_CONTROL0_MSTR_EN 0x00000001 +#define MXC_DSM_CONTROL0_RESTART 0x00000010 +/* Counter Block reset */ +#define MXC_DSM_CONTROL1_CB_RST 0x00000002 +/* State Machine reset */ +#define MXC_DSM_CONTROL1_SM_RST 0x00000004 +/* Bit needed to reset counter block */ +#define MXC_CONTROL1_RST_CNT32 0x00000008 +#define MXC_DSM_CONTROL1_RST_CNT32_EN 0x00000800 +#define MXC_DSM_CONTROL1_SLEEP 0x00000100 +#define MXC_DSM_CONTROL1_WAKEUP_DISABLE 0x00004000 +#define MXC_DSM_CTREN_CNT32 0x00000001 + +/* Magic Fix enable bit */ +#define MXC_DSM_MGPER_EN_MGFX 0x80000000 +#define MXC_DSM_MGPER_PER_MASK 0x000003FF +#define MXC_DSM_MGPER_PER(n) (MXC_DSM_MGPER_PER_MASK & n) + +/* + * Bit definitions of ACGCR in CRM_AP for tree level clock gating + */ +#define MXC_ACGCR_ACG0_STOP_WAIT 0x00000001 +#define MXC_ACGCR_ACG0_STOP 0x00000003 +#define MXC_ACGCR_ACG0_RUN 0x00000007 +#define MXC_ACGCR_ACG0_DISABLED 0x00000000 + +#define MXC_ACGCR_ACG1_STOP_WAIT 0x00000008 +#define MXC_ACGCR_ACG1_STOP 0x00000018 +#define MXC_ACGCR_ACG1_RUN 0x00000038 +#define MXC_ACGCR_ACG1_DISABLED 0x00000000 + +#define MXC_ACGCR_ACG2_STOP_WAIT 0x00000040 +#define MXC_ACGCR_ACG2_STOP 0x000000C0 +#define MXC_ACGCR_ACG2_RUN 0x000001C0 +#define MXC_ACGCR_ACG2_DISABLED 0x00000000 + +#define MXC_ACGCR_ACG3_STOP_WAIT 0x00000200 +#define MXC_ACGCR_ACG3_STOP 0x00000600 +#define MXC_ACGCR_ACG3_RUN 0x00000E00 +#define MXC_ACGCR_ACG3_DISABLED 0x00000000 + +#define MXC_ACGCR_ACG4_STOP_WAIT 0x00001000 +#define MXC_ACGCR_ACG4_STOP 0x00003000 +#define MXC_ACGCR_ACG4_RUN 0x00007000 +#define MXC_ACGCR_ACG4_DISABLED 0x00000000 + +#define MXC_ACGCR_ACG5_STOP_WAIT 0x00010000 +#define MXC_ACGCR_ACG5_STOP 0x00030000 +#define MXC_ACGCR_ACG5_RUN 0x00070000 +#define MXC_ACGCR_ACG5_DISABLED 0x00000000 + +#define MXC_ACGCR_ACG6_STOP_WAIT 0x00080000 +#define MXC_ACGCR_ACG6_STOP 0x00180000 +#define MXC_ACGCR_ACG6_RUN 0x00380000 +#define MXC_ACGCR_ACG6_DISABLED 0x00000000 + +#define NUM_GATE_CTRL 6 + +/* + * Address offsets of the CRM_COM registers + */ +#define CRM_COM_CSCR_PPD1 0x08000000 + +#define MXC_CLKCTL_BASE (IO_ADDRESS(CLKCTL_BASE_ADDR)) + +#define MXC_CLKCTL_GP_CTRL (MXC_CLKCTL_BASE + 0x00) +#define MXC_CLKCTL_GP_SER (MXC_CLKCTL_BASE + 0x04) +#define MXC_CLKCTL_GP_CER (MXC_CLKCTL_BASE + 0x08) + +#define MXC_CLKCTL_GP_CTRL_BIT7 0x80 + +#endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */ diff --git a/arch/arm/mach-scma11/devices.c b/arch/arm/mach-scma11/devices.c new file mode 100644 --- /dev/null +++ b/arch/arm/mach-scma11/devices.c @@ -0,0 +1,251 @@ +/* + * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Sascha Hauer, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +static struct resource uart0[] = { + { + .start = UART1_BASE_ADDR, + .end = UART1_BASE_ADDR + 0x0B5, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_UART1_RX, + .end = MXC_INT_UART1_RX, + .flags = IORESOURCE_IRQ, + }, { + .start = MXC_INT_UART1_TX, + .end = MXC_INT_UART1_TX, + .flags = IORESOURCE_IRQ, + }, { + .start = MXC_INT_UART1_MINT, + .end = MXC_INT_UART1_MINT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_uart_device0 = { + .name = "imx-uart", + .id = 0, + .resource = uart0, + .num_resources = ARRAY_SIZE(uart0), +}; + +static struct resource uart1[] = { + { + .start = UART2_BASE_ADDR, + .end = UART2_BASE_ADDR + 0x0B5, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_UART2_RX, + .end = MXC_INT_UART2_RX, + .flags = IORESOURCE_IRQ, + }, { + .start = MXC_INT_UART2_TX, + .end = MXC_INT_UART2_TX, + .flags = IORESOURCE_IRQ, + }, { + .start = MXC_INT_UART2_MINT, + .end = MXC_INT_UART2_MINT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_uart_device1 = { + .name = "imx-uart", + .id = 1, + .resource = uart1, + .num_resources = ARRAY_SIZE(uart1), +}; + +static struct resource uart2[] = { + { + .start = UART3_BASE_ADDR, + .end = UART3_BASE_ADDR + 0x0B5, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_UART3_RX, + .end = MXC_INT_UART3_RX, + .flags = IORESOURCE_IRQ, + }, { + .start = MXC_INT_UART3_TX, + .end = MXC_INT_UART3_TX, + .flags = IORESOURCE_IRQ, + }, { + .start = MXC_INT_UART3_MINT, + .end = MXC_INT_UART3_MINT, + .flags = IORESOURCE_IRQ, + + }, +}; + +struct platform_device mxc_uart_device2 = { + .name = "imx-uart", + .id = 2, + .resource = uart2, + .num_resources = ARRAY_SIZE(uart2), +}; + +/* GPIO port description */ +static struct mxc_gpio_port mxc_gpio_ports[] = { + [0] = { + .chip.label = "gpio-0", + .base = IO_ADDRESS(GPIO1_AP_BASE_ADDR), + .irq = MXC_INT_GPIO1, + .virtual_irq_start = MXC_GPIO_IRQ_START, + }, + [1] = { + .chip.label = "gpio-1", + .base = IO_ADDRESS(GPIO2_AP_BASE_ADDR), + .irq = MXC_INT_GPIO2, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32, + }, + [2] = { + .chip.label = "gpio-2", + .base = IO_ADDRESS(GPIO3_AP_BASE_ADDR), + .irq = MXC_INT_GPIO3, + .virtual_irq_start = MXC_GPIO_IRQ_START + 64, + }, + [3] = { + .chip.label = "gpio-3", + .base = IO_ADDRESS(GPIO4_SH_BASE_ADDR), + .irq = MXC_INT_GPIO4, + .virtual_irq_start = MXC_GPIO_IRQ_START + 96, + }, +}; + +int __init mxc_register_gpios(void) +{ + return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); +} + +static struct resource mxc_nand_resources[] = { + { + .start = NFC_BASE_ADDR, + .end = NFC_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM + }, { + .start = MXC_INT_NANDFC, + .end = MXC_INT_NANDFC, + .flags = IORESOURCE_IRQ + }, +}; + +struct platform_device mxc_nand_device = { + .name = "mxc_nand", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_nand_resources), + .resource = mxc_nand_resources, +}; + +static struct resource mxc_sdhc0_resources[] = { + { + .start = MMC_SDHC1_BASE_ADDR, + .end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_MMC_SDHC1, + .end = MXC_INT_MMC_SDHC1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource mxc_sdhc1_resources[] = { + { + .start = MMC_SDHC2_BASE_ADDR, + .end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_MMC_SDHC2, + .end = MXC_INT_MMC_SDHC2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_sdhc_device0 = { + .name = "mxc-mmc", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_sdhc0_resources), + .resource = mxc_sdhc0_resources, +}; + +struct platform_device mxc_sdhc_device1 = { + .name = "mxc-mmc", + .id = 1, + .num_resources = ARRAY_SIZE(mxc_sdhc1_resources), + .resource = mxc_sdhc1_resources, +}; + +static struct resource mxc_cspi0_resources[] = { + { + .start = CSPI1_BASE_ADDR, + .end = CSPI1_BASE_ADDR + 0x20, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_CSPI1, + .end = MXC_INT_CSPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_cspi_device0 = { + .name = "spi_imx", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_cspi0_resources), + .resource = mxc_cspi0_resources, +}; + +static struct resource mxc_cspi1_resources[] = { + { + .start = CSPI2_BASE_ADDR, + .end = CSPI2_BASE_ADDR + 0x20, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_CSPI2, + .end = MXC_INT_CSPI2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_cspi_device1 = { + .name = "spi_imx", + .id = 1, + .num_resources = ARRAY_SIZE(mxc_cspi1_resources), + .resource = mxc_cspi1_resources, +}; + +static struct resource mxc_wdog0_resources[] = { + { + .start = WDOG1_BASE_ADDR, + .end = WDOG1_BASE_ADDR + 0x10, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxc_wdog_device0 = { + .name = "scma11-wdt", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_wdog0_resources), + .resource = mxc_wdog0_resources, +}; diff --git a/arch/arm/mach-scma11/devices.h b/arch/arm/mach-scma11/devices.h new file mode 100644 --- /dev/null +++ b/arch/arm/mach-scma11/devices.h @@ -0,0 +1,17 @@ +#ifndef __ARCH_ARM_MACH_SCMA11_DEVICES_H__ +#define __ARCH_ARM_MACH_SCMA11_DEVICES_H__ + +extern struct platform_device mxc_uart_device0; +extern struct platform_device mxc_uart_device1; +extern struct platform_device mxc_uart_device2; + +extern struct platform_device mxc_nand_device; + +extern struct platform_device mxc_sdhc_device0; +extern struct platform_device mxc_sdhc_device1; + +extern struct platform_device mxc_cspi_device0; +extern struct platform_device mxc_cspi_device1; + +extern struct platform_device mxc_wdog_device0; +#endif diff --git a/arch/arm/mach-scma11/iomux.c b/arch/arm/mach-scma11/iomux.c new file mode 100644 --- /dev/null +++ b/arch/arm/mach-scma11/iomux.c @@ -0,0 +1,180 @@ +/* + * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008 by Sascha Hauer + * Copyright (C) 2009 by Valentin Longchamp + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * IOMUX register (base) addresses + */ +#define IOMUX_AP_BASE IO_ADDRESS(IOMUX_AP_BASE_ADDR) +#define IOMUX_COM_BASE IO_ADDRESS(IOMUX_COM_BASE_ADDR) +#define IOMUXSW_AP_MUX_CTL (IOMUX_AP_BASE + 0x000) +#define IOMUXSW_SP_MUX_CTL (IOMUX_COM_BASE + 0x000) +#define IOMUXSW_PAD_CTL (IOMUX_COM_BASE + 0x200) + +#define IOMUXINT_OBS1 (IOMUX_AP_BASE + 0x600) +#define IOMUXINT_OBS2 (IOMUX_AP_BASE + 0x004) + +static DEFINE_SPINLOCK(gpio_mux_lock); + +#define NB_PORTS ((PIN_MAX + 32) / 32) +#define PIN_GLOBAL_NUM(pin) \ + (((pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT)*PIN_AP_MAX + \ + ((pin & MUX_REG_MASK) >> MUX_REG_SHIFT)*4 + \ + ((pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT)) +#define UNSTUFF_PIN(pin_mode) (pin_mode & MUX_PIN_MASK) +#define UNSTUFF_MODE(pin_mode) ((pin_mode & MUX_MODE_MASK) >> MUX_MODE_SHIFT) + +unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG]; +/* + * set the mode for a IOMUX pin. + */ +int mxc_iomux_mode(const unsigned int pin_mode) +{ + u32 pin, side, field, l, mode, ret = 0; + void __iomem *reg; + + pin = UNSTUFF_PIN(pin_mode); + mode = UNSTUFF_MODE(pin_mode); + + side = (pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT; + switch (side) { + case MUX_SIDE_AP: + reg = IOMUXSW_AP_MUX_CTL; + break; + case MUX_SIDE_SP: + reg = IOMUXSW_SP_MUX_CTL; + break; + default: + return -EINVAL; + } + reg += ((pin & MUX_REG_MASK) >> MUX_REG_SHIFT) * 4; + field = (pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT; + spin_lock(&gpio_mux_lock); + + l = __raw_readl(reg); + l &= ~(0xff << (field * 8)); + l |= mode << (field * 8); + __raw_writel(l, reg); + + spin_unlock(&gpio_mux_lock); + + return ret; +} +EXPORT_SYMBOL(mxc_iomux_mode); + +/* + * This function configures the pad value for a IOMUX pin. + */ +void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) +{ + u32 padgrp, field, l; + void __iomem *reg; + + padgrp = (pin & MUX_PADGRP_MASK) >> MUX_PADGRP_SHIFT; + reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4; + field = (pin + 2) % 3; + + pr_debug("%s: reg offset = 0x%x, field = %d\n", + __func__, (pin + 2) / 3, field); + + spin_lock(&gpio_mux_lock); + + l = __raw_readl(reg); + l &= ~(0x1ff << (field * 10)); + l |= config << (field * 10); + __raw_writel(l, reg); + + spin_unlock(&gpio_mux_lock); +} +EXPORT_SYMBOL(mxc_iomux_set_pad); + +/* + * allocs a single pin: + * - reserves the pin so that it is not claimed by another driver + * - setups the iomux according to the configuration + */ +int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label) +{ + unsigned pad = PIN_GLOBAL_NUM(UNSTUFF_PIN(pin_mode)); + if (pad >= (PIN_MAX + 1)) { + printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n", + pad, label ? label : "?"); + return -EINVAL; + } + + if (test_and_set_bit(pad, mxc_pin_alloc_map)) { + printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n", + pad, label ? label : "?"); + return -EBUSY; + } + mxc_iomux_mode(pin_mode); + + return 0; +} +EXPORT_SYMBOL(mxc_iomux_alloc_pin); + +int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, + const char *label) +{ + unsigned int *p = pin_list; + int i; + int ret = -EINVAL; + + for (i = 0; i < count; i++) { + ret = mxc_iomux_alloc_pin(*p, label); + if (ret) + goto setup_error; + p++; + } + return 0; + +setup_error: + mxc_iomux_release_multiple_pins(pin_list, i); + return ret; +} +EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); + +void mxc_iomux_release_pin(const unsigned int pin_mode) +{ + unsigned pad = PIN_GLOBAL_NUM(UNSTUFF_PIN(pin_mode)); + + if (pad < (PIN_MAX + 1)) + clear_bit(pad, mxc_pin_alloc_map); +} +EXPORT_SYMBOL(mxc_iomux_release_pin); + +void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count) +{ + unsigned int *p = pin_list; + int i; + + for (i = 0; i < count; i++) { + mxc_iomux_release_pin(*p); + p++; + } +} +EXPORT_SYMBOL(mxc_iomux_release_multiple_pins); diff --git a/arch/arm/mach-scma11/magx-e8.c b/arch/arm/mach-scma11/magx-e8.c new file mode 100644 --- /dev/null +++ b/arch/arm/mach-scma11/magx-e8.c @@ -0,0 +1,25 @@ +#include +#include +#include + +#include +#include + +#include "devices.h" +#include "scma11phone.h" + +static void __init e8_init(void) +{ + scma11_init(); + return; +} + +MACHINE_START(MAGX_E8, "Motorola E8") + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = scma11_map_io, + .init_irq = mxc_init_irq, + .timer = &scma11_timer, + .init_machine = e8_init, +MACHINE_END diff --git a/arch/arm/mach-scma11/magx-zn5.c b/arch/arm/mach-scma11/magx-zn5.c new file mode 100644 --- /dev/null +++ b/arch/arm/mach-scma11/magx-zn5.c @@ -0,0 +1,56 @@ +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "devices.h" +#include "scma11phone.h" + +static struct spi_imx_chip zn5_atlas_chipinfo = { + .ins_ss_pulse = 1, +}; + +static struct spi_board_info zn5_spi_boardinfo[] __initdata = { + { + .modalias = "atlas", + .bus_num = 1, + .chip_select = 2, + .max_speed_hz = 4200000, + .platform_data = NULL, + .controller_data = &zn5_atlas_chipinfo, + .mode = SPI_MODE_0 | SPI_CS_HIGH, + }, +}; + +static struct imxmmc_platform_data sdhc_pdata = { +}; + +static void __init zn5_init(void) +{ + scma11_init(); + + mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata); + spi_register_board_info(zn5_spi_boardinfo, + ARRAY_SIZE(zn5_spi_boardinfo)); + return; +} + +MACHINE_START(MAGX_ZN5, "Motorola Zn5") + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = scma11_map_io, + .init_irq = mxc_init_irq, + .timer = &scma11_timer, + .init_machine = zn5_init, +MACHINE_END diff --git a/arch/arm/mach-scma11/mm.c b/arch/arm/mach-scma11/mm.c new file mode 100644 --- /dev/null +++ b/arch/arm/mach-scma11/mm.c @@ -0,0 +1,93 @@ +/* + * Copyright (C) 1999,2000 Arm Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright 2004-2005 Freescale Semiconductor, Inc. All Rights Reserved. + * - add MXC specific definitions + * Copyright 2006 Motorola, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Date Author Comment + * 10/2006 Motorola Added Motorola product specific additions to the + * MXC memory map structure + * + */ + +#include +#include +#include +#include +#include +#include + +/* + * This structure defines the MXC memory map. + */ +static struct map_desc mxc_io_desc[] __initdata = { + { + .virtual = L2CC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(L2CC_BASE_ADDR), + .length = L2CC_SIZE, + .type = MT_DEVICE, + }, { + .virtual = X_MEMC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), + .length = X_MEMC_SIZE, + .type = MT_DEVICE, + }, { + .virtual = ROMP_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(ROMP_BASE_ADDR), + .length = ROMP_SIZE, + .type = MT_DEVICE, + }, { + .virtual = AVIC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AVIC_BASE_ADDR), + .length = AVIC_SIZE, + .type = MT_DEVICE, + }, { + .virtual = AIPS1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), + .length = AIPS1_SIZE, + .type = MT_DEVICE, + }, { + .virtual = SPBA0_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), + .length = SPBA0_SIZE, + .type = MT_DEVICE, + }, { + .virtual = SPBA1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(SPBA1_BASE_ADDR), + .length = SPBA1_SIZE, + .type = MT_DEVICE, + }, { + .virtual = AIPS2_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), + .length = AIPS2_SIZE, + .type = MT_DEVICE, + }, +}; + +/* + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory map for + * the IO modules. + */ +void __init scma11_map_io(void) +{ + mxc_set_cpu_type(MXC_CPU_SCMA11); + + iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); +} diff --git a/arch/arm/mach-scma11/scma11phone.c b/arch/arm/mach-scma11/scma11phone.c new file mode 100644 --- /dev/null +++ b/arch/arm/mach-scma11/scma11phone.c @@ -0,0 +1,89 @@ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +#define WDOG_WCR (IO_ADDRESS(WDOG1_BASE_ADDR)) +#define WDOG_WCR_OUT_ENABLE (1 << 6) +#define WDOG_WCR_ASSERT (1 << 5) + +#define CRM_AP_AMCR (IO_ADDRESS(CRM_AP_BASE_ADDR)+0x48) +#define CRM_AP_AMCR_SW_AP (1 << 14) + +static struct imxuart_platform_data uart_pdata = { +}; + +static struct spi_imx_master spi_pdata = { + .num_chipselect = 3, + .enable_dma = 0, +}; + +/* static struct imxmmc_platform_data sdhc_pdata = { */ +/* }; */ + +static void scma11_power_off(void) +{ + u16 wcr; + + wcr = __raw_readw(WDOG_WCR); + wcr |= WDOG_WCR_OUT_ENABLE; + wcr &= ~WDOG_WCR_ASSERT; + __raw_writew(wcr, WDOG_WCR); +} + +void arch_reset(char mode, const char *cmd) +{ + u32 amcr; + + amcr = __raw_readl(CRM_AP_AMCR); + amcr &= ~CRM_AP_AMCR_SW_AP; + __raw_writel(amcr, CRM_AP_AMCR); + + mdelay(10); + cpu_reset(0); +} + +void __init scma11_init(void) +{ + pm_power_off = scma11_power_off; + + mxc_iomux_alloc_pin(IOMUX_MODE(SCMA11_PIN_SP_USB_DAT_VP, + IOMUX_ICONFIG_ALT2, + IOMUX_OCONFIG_ALT2), "uart2-rx"); + mxc_iomux_alloc_pin(IOMUX_MODE(SCMA11_PIN_SP_USB_SE0_VM, + IOMUX_ICONFIG_ALT2, + IOMUX_OCONFIG_ALT2), "uart2-tx"); + +/* TODO: the order is important if you are using console=ttymxc1. need + * to figure out why. */ + mxc_register_device(&mxc_uart_device1, &uart_pdata); + mxc_register_device(&mxc_uart_device0, &uart_pdata); + mxc_register_device(&mxc_cspi_device0, &spi_pdata); + mxc_register_device(&mxc_cspi_device1, &spi_pdata); + mxc_register_device(&mxc_wdog_device0, NULL); +}; + +static void __init scma11_timer_init(void) +{ + scma11_clocks_init(26000000); /* 26mhz ckih */ +} + +struct sys_timer scma11_timer = { + .init = scma11_timer_init, +}; diff --git a/arch/arm/mach-scma11/scma11phone.h b/arch/arm/mach-scma11/scma11phone.h new file mode 100644 --- /dev/null +++ b/arch/arm/mach-scma11/scma11phone.h @@ -0,0 +1,10 @@ +#ifndef __ARCH_ARM_MACH_SCMA11_SCMA11PHONE_H__ +#define __ARCH_ARM_MACH_SCMA11_SCMA11PHONE_H__ + +struct sys_timer; + +void scma11_init(void); + +extern struct sys_timer scma11_timer; + +#endif diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -758,7 +758,7 @@ config CACHE_L2X0 bool "Enable the L2x0 outer cache controller" depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ - REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX + REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_SCMA11 default y select OUTER_CACHE help diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -26,11 +26,19 @@ help This enables support for systems based on the Freescale i.MX3 family +config ARCH_SCMA11 + bool "Freescale SCMA11" + select CPU_V6 + select COMMON_CLKDEV + help + This enables support for systems based on the Freescale MXC91231 family + endchoice source "arch/arm/mach-mx1/Kconfig" source "arch/arm/mach-mx2/Kconfig" source "arch/arm/mach-mx3/Kconfig" +source "arch/arm/mach-scma11/Kconfig" endmenu diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -162,8 +162,8 @@ } } -#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1) -/* MX1 and MX3 has one interrupt *per* gpio port */ +#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1) || defined(CONFIG_ARCH_SCMA11) +/* MX1, MX3 and SCMA11 has one interrupt *per* gpio port */ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) { u32 irq_stat; @@ -284,7 +284,7 @@ /* its a serious configuration bug when it fails */ BUG_ON( gpiochip_add(&port[i].chip) < 0 ); -#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1) +#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1) || defined(CONFIG_ARCH_SCMA11) /* setup one handler for each entry */ set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); set_irq_data(port[i].irq, &port[i]); diff --git a/arch/arm/plat-mxc/include/mach/board-scma11.h b/arch/arm/plat-mxc/include/mach/board-scma11.h new file mode 100644 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-scma11.h @@ -0,0 +1,19 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_BOARD_SCMA11_H__ +#define __ASM_ARCH_MXC_BOARD_SCMA11_H__ + +/* mandatory for CONFIG_LL_DEBUG */ + +#define MXC_LL_UART_PADDR UART2_BASE_ADDR +#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART2_BASE_ADDR) + +#endif /* __ASM_ARCH_MXC_BOARD_SCMA11_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -19,6 +19,7 @@ extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); +extern void scma11_map_io(void); extern void mxc_init_irq(void); extern void mxc_timer_init(struct clk *timer_clk); extern int mx1_clocks_init(unsigned long fref); @@ -26,6 +27,7 @@ extern int mx27_clocks_init(unsigned long fref); extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); +extern int scma11_clocks_init(unsigned long fref); extern int mxc_register_gpios(void); extern int mxc_register_device(struct platform_device *pdev, void *data); extern void mxc_set_cpu_type(unsigned int type); diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -52,6 +52,9 @@ #ifdef CONFIG_MACH_MX27LITE #include #endif +#ifdef CONFIG_ARCH_SCMA11 +#include +#endif .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -42,6 +42,10 @@ # include #endif +#ifdef CONFIG_ARCH_SCMA11 +# include +#endif + #include #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-scma11.h b/arch/arm/plat-mxc/include/mach/iomux-scma11.h new file mode 100644 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-scma11.h @@ -0,0 +1,262 @@ +/* + * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008 by Sascha Hauer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __MACH_IOMUX_SCMA11_H__ +#define __MACH_IOMUX_SCMA11_H__ + + +#define IOMUX_OCONFIG_GPIO (0) /* used as GPIO */ +#define IOMUX_OCONFIG_ALT1 (1) /* used as alternate function 1 */ +#define IOMUX_OCONFIG_ALT2 (2) /* used as alternate function 2 */ +#define IOMUX_OCONFIG_ALT3 (3) /* used as alternate function 3 */ +#define IOMUX_OCONFIG_ALT4 (4) /* used as alternate function 4 */ +#define IOMUX_OCONFIG_ALT5 (5) /* used as alternate function 5 */ +#define IOMUX_OCONFIG_ALT6 (6) /* used as alternate function 6 */ +#define IOMUX_OCONFIG_ALT7 (7) /* used as alternate function 7 */ +#define IOMUX_ICONFIG_NONE (0) /* not configured for input */ +#define IOMUX_ICONFIG_GPIO (1) /* used as GPIO */ +#define IOMUX_ICONFIG_ALT1 (2) /* used as alternate function 1 */ +#define IOMUX_ICONFIG_ALT2 (4) /* used as alternate function 2 */ +#define IOMUX_ICONFIG_ALT3 (8) /* used as alternate function 3 */ + +/* + * setups a single pin: + * - reserves the pin so that it is not claimed by another driver + * - setups the iomux according to the configuration + * - if the pin is configured as a GPIO, we claim it throug kernel gpiolib + */ +int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label); +/* + * setups mutliple pins + * convenient way to call the above function with tables + */ +int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, + const char *label); + +/* + * releases a single pin: + * - make it available for a future use by another driver + * - frees the GPIO if the pin was configured as GPIO + * - DOES NOT reconfigure the IOMUX in its reset state + */ +void mxc_iomux_release_pin(const unsigned int pin_mode); +/* + * releases multiple pins + * convenvient way to call the above function with tables + */ +void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count); + +#define MUX_SIDE_AP (0) +#define MUX_SIDE_SP (1) + +#define MUX_SIDE_SHIFT (26) +#define MUX_SIDE_MASK (0x1 << MUX_SIDE_SHIFT) + +#define MUX_GPIO_PORT_SHIFT (23) +#define MUX_GPIO_PORT_MASK (0x7 << MUX_GPIO_PORT_SHIFT) + +#define MUX_GPIO_PIN_SHIFT (20) +#define MUX_GPIO_PIN_MASK (0x1f << MUX_GPIO_PIN_SHIFT) + +#define MUX_REG_SHIFT (15) +#define MUX_REG_MASK (0x1f << MUX_REG_SHIFT) + +#define MUX_FIELD_SHIFT (13) +#define MUX_FIELD_MASK (0x3 << MUX_FIELD_SHIFT) + +#define MUX_PADGRP_SHIFT (8) +#define MUX_PADGRP_MASK (0x1f << MUX_PADGRP_SHIFT) + +#define MUX_PIN_MASK (0xffffff << 8) + +#define GPIO_PORT_MAX (3) + +#define IOMUX_PIN(side,gport,gpin,ctlreg,ctlfield,padgrp) \ + (((side) << MUX_SIDE_SHIFT) | \ + (gport << MUX_GPIO_PORT_SHIFT) | \ + ((gpin) << MUX_GPIO_PIN_SHIFT) | \ + ((ctlreg) << MUX_REG_SHIFT) | \ + ((ctlfield) << MUX_FIELD_SHIFT) | \ + ((padgrp) << MUX_PADGRP_SHIFT)) + +#define MUX_MODE_OUT_SHIFT (4) +#define MUX_MODE_IN_SHIFT (0) +#define MUX_MODE_SHIFT (0) +#define MUX_MODE_MASK (0xff << MUX_MODE_SHIFT) + +#define IOMUX_MODE(pin, in, out) \ + (pin | (out << MUX_MODE_OUT_SHIFT) | (in << MUX_MODE_IN_SHIFT)) + +enum iomux_pins { + /* AP Side pins */ + SCMA11_PIN_AP_CLE = IOMUX_PIN(0, 0, 0, 0, 0, 24), + SCMA11_PIN_AP_ALE = IOMUX_PIN(0, 0, 1, 0, 1, 24), + SCMA11_PIN_AP_CE_B = IOMUX_PIN(0, 0, 2, 0, 2, 24), + SCMA11_PIN_AP_RE_B = IOMUX_PIN(0, 0, 3, 0, 3, 24), + SCMA11_PIN_AP_WE_B = IOMUX_PIN(0, 0, 4, 1, 0, 24), + SCMA11_PIN_AP_WP_B = IOMUX_PIN(0, 0, 5, 1, 1, 24), + SCMA11_PIN_AP_BSY_B = IOMUX_PIN(0, 0, 6, 1, 2, 24), + SCMA11_PIN_AP_U1_TXD = IOMUX_PIN(0, 0, 7, 1, 3, 28), + SCMA11_PIN_AP_U1_RXD = IOMUX_PIN(0, 0, 8, 2, 0, 28), + SCMA11_PIN_AP_U1_RTS_B = IOMUX_PIN(0, 0, 9, 2, 1, 28), + SCMA11_PIN_AP_U1_CTS_B = IOMUX_PIN(0, 0, 10, 2, 2, 28), + SCMA11_PIN_AP_AD1_TXD = IOMUX_PIN(0, 0, 11, 2, 3, 9), + SCMA11_PIN_AP_AD1_RXD = IOMUX_PIN(0, 0, 12, 3, 0, 9), + SCMA11_PIN_AP_AD1_TXC = IOMUX_PIN(0, 0, 13, 3, 1, 9), + SCMA11_PIN_AP_AD1_TXFS = IOMUX_PIN(0, 0, 14, 3, 2, 9), + SCMA11_PIN_AP_AD2_TXD = IOMUX_PIN(0, 0, 15, 3, 3, 9), + SCMA11_PIN_AP_AD2_RXD = IOMUX_PIN(0, 0, 16, 4, 0, 9), + SCMA11_PIN_AP_AD2_TXC = IOMUX_PIN(0, 0, 17, 4, 1, 9), + SCMA11_PIN_AP_AD2_TXFS = IOMUX_PIN(0, 0, 18, 4, 2, 9), + SCMA11_PIN_AP_OWDAT = IOMUX_PIN(0, 0, 19, 4, 3, 28), + SCMA11_PIN_AP_IPU_LD17 = IOMUX_PIN(0, 0, 20, 5, 0, 28), + SCMA11_PIN_AP_IPU_D3_VSYNC = IOMUX_PIN(0, 0, 21, 5, 1, 28), + SCMA11_PIN_AP_IPU_D3_HSYNC = IOMUX_PIN(0, 0, 22, 5, 2, 28), + SCMA11_PIN_AP_IPU_D3_CLK = IOMUX_PIN(0, 0, 23, 5, 3, 28), + SCMA11_PIN_AP_IPU_D3_DRDY = IOMUX_PIN(0, 0, 24, 6, 0, 28), + SCMA11_PIN_AP_IPU_D3_CONTR = IOMUX_PIN(0, 0, 25, 6, 1, 28), + SCMA11_PIN_AP_IPU_D0_CS = IOMUX_PIN(0, 0, 26, 6, 2, 28), + SCMA11_PIN_AP_IPU_LD16 = IOMUX_PIN(0, 0, 27, 6, 3, 28), + SCMA11_PIN_AP_IPU_D2_CS = IOMUX_PIN(0, 0, 28, 7, 0, 28), + SCMA11_PIN_AP_IPU_PAR_RS = IOMUX_PIN(0, 0, 29, 7, 1, 28), + SCMA11_PIN_AP_IPU_D3_PS = IOMUX_PIN(0, 0, 30, 7, 2, 28), + SCMA11_PIN_AP_IPU_D3_CLS = IOMUX_PIN(0, 0, 31, 7, 3, 28), + SCMA11_PIN_AP_IPU_RD = IOMUX_PIN(0, 1, 0, 8, 0, 28), + SCMA11_PIN_AP_IPU_WR = IOMUX_PIN(0, 1, 1, 8, 1, 28), + SCMA11_PIN_AP_IPU_LD0 = IOMUX_PIN(0, 7, 0, 8, 2, 28), + SCMA11_PIN_AP_IPU_LD1 = IOMUX_PIN(0, 7, 0, 8, 3, 28), + SCMA11_PIN_AP_IPU_LD2 = IOMUX_PIN(0, 7, 0, 9, 0, 28), + SCMA11_PIN_AP_IPU_LD3 = IOMUX_PIN(0, 1, 2, 9, 1, 28), + SCMA11_PIN_AP_IPU_LD4 = IOMUX_PIN(0, 1, 3, 9, 2, 28), + SCMA11_PIN_AP_IPU_LD5 = IOMUX_PIN(0, 1, 4, 9, 3, 28), + SCMA11_PIN_AP_IPU_LD6 = IOMUX_PIN(0, 1, 5, 10, 0, 28), + SCMA11_PIN_AP_IPU_LD7 = IOMUX_PIN(0, 1, 6, 10, 1, 28), + SCMA11_PIN_AP_IPU_LD8 = IOMUX_PIN(0, 1, 7, 10, 2, 28), + SCMA11_PIN_AP_IPU_LD9 = IOMUX_PIN(0, 1, 8, 10, 3, 28), + SCMA11_PIN_AP_IPU_LD10 = IOMUX_PIN(0, 1, 9, 11, 0, 28), + SCMA11_PIN_AP_IPU_LD11 = IOMUX_PIN(0, 1, 10, 11, 1, 28), + SCMA11_PIN_AP_IPU_LD12 = IOMUX_PIN(0, 1, 11, 11, 2, 28), + SCMA11_PIN_AP_IPU_LD13 = IOMUX_PIN(0, 1, 12, 11, 3, 28), + SCMA11_PIN_AP_IPU_LD14 = IOMUX_PIN(0, 1, 13, 12, 0, 28), + SCMA11_PIN_AP_IPU_LD15 = IOMUX_PIN(0, 1, 14, 12, 1, 28), + SCMA11_PIN_AP_KPROW4 = IOMUX_PIN(0, 7, 0, 12, 2, 10), + SCMA11_PIN_AP_KPROW5 = IOMUX_PIN(0, 1, 16, 12, 3, 10), + SCMA11_PIN_AP_GPIO_AP_B17 = IOMUX_PIN(0, 1, 17, 13, 0, 10), + SCMA11_PIN_AP_GPIO_AP_B18 = IOMUX_PIN(0, 1, 18, 13, 1, 10), + SCMA11_PIN_AP_KPCOL3 = IOMUX_PIN(0, 1, 19, 13, 2, 11), + SCMA11_PIN_AP_KPCOL4 = IOMUX_PIN(0, 1, 20, 13, 3, 11), + SCMA11_PIN_AP_KPCOL5 = IOMUX_PIN(0, 1, 21, 14, 0, 11), + SCMA11_PIN_AP_GPIO_AP_B22 = IOMUX_PIN(0, 1, 22, 14, 1, 11), + SCMA11_PIN_AP_GPIO_AP_B23 = IOMUX_PIN(0, 1, 23, 14, 2, 11), + SCMA11_PIN_AP_CSI_D0 = IOMUX_PIN(0, 1, 24, 14, 3, 21), + SCMA11_PIN_AP_CSI_D1 = IOMUX_PIN(0, 1, 25, 15, 0, 21), + SCMA11_PIN_AP_CSI_D2 = IOMUX_PIN(0, 1, 26, 15, 1, 21), + SCMA11_PIN_AP_CSI_D3 = IOMUX_PIN(0, 1, 27, 15, 2, 21), + SCMA11_PIN_AP_CSI_D4 = IOMUX_PIN(0, 1, 28, 15, 3, 21), + SCMA11_PIN_AP_CSI_D5 = IOMUX_PIN(0, 1, 29, 16, 0, 21), + SCMA11_PIN_AP_CSI_D6 = IOMUX_PIN(0, 1, 30, 16, 1, 21), + SCMA11_PIN_AP_CSI_D7 = IOMUX_PIN(0, 1, 31, 16, 2, 21), + SCMA11_PIN_AP_CSI_D8 = IOMUX_PIN(0, 2, 0, 16, 3, 21), + SCMA11_PIN_AP_CSI_D9 = IOMUX_PIN(0, 2, 1, 17, 0, 21), + SCMA11_PIN_AP_CSI_MCLK = IOMUX_PIN(0, 2, 2, 17, 1, 21), + SCMA11_PIN_AP_CSI_VSYNC = IOMUX_PIN(0, 2, 3, 17, 2, 21), + SCMA11_PIN_AP_CSI_HSYNC = IOMUX_PIN(0, 2, 4, 17, 3, 21), + SCMA11_PIN_AP_CSI_PIXCLK = IOMUX_PIN(0, 2, 5, 18, 0, 21), + SCMA11_PIN_AP_I2CLK = IOMUX_PIN(0, 2, 6, 18, 1, 12), + SCMA11_PIN_AP_I2DAT = IOMUX_PIN(0, 2, 7, 18, 2, 12), + SCMA11_PIN_AP_GPIO_AP_C8 = IOMUX_PIN(0, 2, 8, 18, 3, 9), + SCMA11_PIN_AP_GPIO_AP_C9 = IOMUX_PIN(0, 2, 9, 19, 0, 9), + SCMA11_PIN_AP_GPIO_AP_C10 = IOMUX_PIN(0, 2, 10, 19, 1, 9), + SCMA11_PIN_AP_GPIO_AP_C11 = IOMUX_PIN(0, 2, 11, 19, 2, 9), + SCMA11_PIN_AP_GPIO_AP_C12 = IOMUX_PIN(0, 2, 12, 19, 3, 9), + SCMA11_PIN_AP_GPIO_AP_C13 = IOMUX_PIN(0, 2, 13, 20, 0, 28), + SCMA11_PIN_AP_GPIO_AP_C14 = IOMUX_PIN(0, 2, 14, 20, 1, 28), + SCMA11_PIN_AP_GPIO_AP_C15 = IOMUX_PIN(0, 2, 15, 20, 2, 9), + SCMA11_PIN_AP_GPIO_AP_C16 = IOMUX_PIN(0, 2, 16, 20, 3, 9), + SCMA11_PIN_AP_GPIO_AP_C17 = IOMUX_PIN(0, 2, 17, 21, 0, 9), + SCMA11_PIN_AP_ED_INT0 = IOMUX_PIN(0, 2, 18, 21, 1, 22), + SCMA11_PIN_AP_ED_INT1 = IOMUX_PIN(0, 2, 19, 21, 2, 22), + SCMA11_PIN_AP_ED_INT2 = IOMUX_PIN(0, 2, 20, 21, 3, 22), + SCMA11_PIN_AP_ED_INT3 = IOMUX_PIN(0, 2, 21, 22, 0, 22), + SCMA11_PIN_AP_ED_INT4 = IOMUX_PIN(0, 2, 22, 22, 1, 23), + SCMA11_PIN_AP_ED_INT5 = IOMUX_PIN(0, 2, 23, 22, 2, 23), + SCMA11_PIN_AP_ED_INT6 = IOMUX_PIN(0, 2, 24, 22, 3, 23), + SCMA11_PIN_AP_ED_INT7 = IOMUX_PIN(0, 2, 25, 23, 0, 23), + SCMA11_PIN_AP_U2_DSR_B = IOMUX_PIN(0, 2, 26, 23, 1, 28), + SCMA11_PIN_AP_U2_RI_B = IOMUX_PIN(0, 2, 27, 23, 2, 28), + SCMA11_PIN_AP_U2_CTS_B = IOMUX_PIN(0, 2, 28, 23, 3, 28), + SCMA11_PIN_AP_U2_DTR_B = IOMUX_PIN(0, 2, 29, 24, 0, 28), + SCMA11_PIN_AP_KPROW0 = IOMUX_PIN(0, 7, 0, 24, 1, 10), + SCMA11_PIN_AP_KPROW1 = IOMUX_PIN(0, 1, 15, 24, 2, 10), + SCMA11_PIN_AP_KPROW2 = IOMUX_PIN(0, 7, 0, 24, 3, 10), + SCMA11_PIN_AP_KPROW3 = IOMUX_PIN(0, 7, 0, 25, 0, 10), + SCMA11_PIN_AP_KPCOL0 = IOMUX_PIN(0, 7, 0, 25, 1, 11), + SCMA11_PIN_AP_KPCOL1 = IOMUX_PIN(0, 7, 0, 25, 2, 11), + SCMA11_PIN_AP_KPCOL2 = IOMUX_PIN(0, 7, 0, 25, 3, 11), + + /* Shared pins */ + SCMA11_PIN_SP_U3_TXD = IOMUX_PIN(1, 3, 0, 0, 0, 28), + SCMA11_PIN_SP_U3_RXD = IOMUX_PIN(1, 3, 1, 0, 1, 28), + SCMA11_PIN_SP_U3_RTS_B = IOMUX_PIN(1, 3, 2, 0, 2, 28), + SCMA11_PIN_SP_U3_CTS_B = IOMUX_PIN(1, 3, 3, 0, 3, 28), + SCMA11_PIN_SP_USB_TXOE_B = IOMUX_PIN(1, 3, 4, 1, 0, 28), + SCMA11_PIN_SP_USB_DAT_VP = IOMUX_PIN(1, 3, 5, 1, 1, 28), + SCMA11_PIN_SP_USB_SE0_VM = IOMUX_PIN(1, 3, 6, 1, 2, 28), + SCMA11_PIN_SP_USB_RXD = IOMUX_PIN(1, 3, 7, 1, 3, 28), + SCMA11_PIN_SP_UH2_TXOE_B = IOMUX_PIN(1, 3, 8, 2, 0, 28), + SCMA11_PIN_SP_UH2_SPEED = IOMUX_PIN(1, 3, 9, 2, 1, 28), + SCMA11_PIN_SP_UH2_SUSPEN = IOMUX_PIN(1, 3, 10, 2, 2, 28), + SCMA11_PIN_SP_UH2_TXDP = IOMUX_PIN(1, 3, 11, 2, 3, 28), + SCMA11_PIN_SP_UH2_RXDP = IOMUX_PIN(1, 3, 12, 3, 0, 28), + SCMA11_PIN_SP_UH2_RXDM = IOMUX_PIN(1, 3, 13, 3, 1, 28), + SCMA11_PIN_SP_UH2_OVR = IOMUX_PIN(1, 3, 14, 3, 2, 28), + SCMA11_PIN_SP_UH2_PWR = IOMUX_PIN(1, 3, 15, 3, 3, 28), + SCMA11_PIN_SP_SD1_DAT0 = IOMUX_PIN(1, 3, 16, 4, 0, 25), + SCMA11_PIN_SP_SD1_DAT1 = IOMUX_PIN(1, 3, 17, 4, 1, 25), + SCMA11_PIN_SP_SD1_DAT2 = IOMUX_PIN(1, 3, 18, 4, 2, 25), + SCMA11_PIN_SP_SD1_DAT3 = IOMUX_PIN(1, 3, 19, 4, 3, 25), + SCMA11_PIN_SP_SD1_CMD = IOMUX_PIN(1, 3, 20, 5, 0, 25), + SCMA11_PIN_SP_SD1_CLK = IOMUX_PIN(1, 3, 21, 5, 1, 25), + SCMA11_PIN_SP_SD2_DAT0 = IOMUX_PIN(1, 3, 22, 5, 2, 26), + SCMA11_PIN_SP_SD2_DAT1 = IOMUX_PIN(1, 3, 23, 5, 3, 26), + SCMA11_PIN_SP_SD2_DAT2 = IOMUX_PIN(1, 3, 24, 6, 0, 26), + SCMA11_PIN_SP_SD2_DAT3 = IOMUX_PIN(1, 3, 25, 6, 1, 26), + SCMA11_PIN_SP_GPIO_SP_A26 = IOMUX_PIN(1, 3, 26, 6, 2, 28), + SCMA11_PIN_SP_SPI1_CLK = IOMUX_PIN(1, 3, 27, 6, 3, 13), + SCMA11_PIN_SP_SPI1_MOSI = IOMUX_PIN(1, 3, 28, 7, 0, 13), + SCMA11_PIN_SP_SPI1_MISO = IOMUX_PIN(1, 3, 29, 7, 1, 13), + SCMA11_PIN_SP_SPI1_SS0 = IOMUX_PIN(1, 3, 30, 7, 2, 13), + SCMA11_PIN_SP_SPI1_SS1 = IOMUX_PIN(1, 3, 31, 7, 3, 13), + SCMA11_PIN_SP_SD2_CMD = IOMUX_PIN(1, 7, 0, 8, 0, 26), + SCMA11_PIN_SP_SD2_CLK = IOMUX_PIN(1, 7, 0, 8, 1, 26), + SCMA11_PIN_SP_SIM1_RST_B = IOMUX_PIN(1, 2, 30, 8, 2, 28), + SCMA11_PIN_SP_SIM1_SVEN = IOMUX_PIN(1, 7, 0, 8, 3, 28), + SCMA11_PIN_SP_SIM1_CLK = IOMUX_PIN(1, 7, 0, 9, 0, 28), + SCMA11_PIN_SP_SIM1_TRXD = IOMUX_PIN(1, 7, 0, 9, 1, 28), + SCMA11_PIN_SP_SIM1_PD = IOMUX_PIN(1, 2, 31, 9, 2, 28), + SCMA11_PIN_SP_UH2_TXDM = IOMUX_PIN(1, 7, 0, 9, 3, 28), + SCMA11_PIN_SP_UH2_RXD = IOMUX_PIN(1, 7, 0, 10, 0, 28), +}; + +#define PIN_AP_MAX (104) +#define PIN_SP_MAX (41) + +#define PIN_MAX (PIN_AP_MAX + PIN_SP_MAX) + +#endif /* __MACH_IOMUX_SCMA11_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -24,6 +24,8 @@ #define MXC_GPIO_IRQS (32 * 6) #elif defined CONFIG_ARCH_MX3 #define MXC_GPIO_IRQS (32 * 3) +#elif defined CONFIG_ARCH_SCMA11 +#define MXC_GPIO_IRQS (32 * 4) #endif /* diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -22,6 +22,8 @@ #endif #elif defined CONFIG_ARCH_MX3 #define PHYS_OFFSET UL(0x80000000) +#elif defined CONFIG_ARCH_SCMA11 +#define PHYS_OFFSET UL(0x90000000) #endif #if defined(CONFIG_MX1_VIDEO) diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -29,6 +29,7 @@ #define MXC_CPU_MX27 27 #define MXC_CPU_MX31 31 #define MXC_CPU_MX35 35 +#define MXC_CPU_SCMA11 11 #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; @@ -94,6 +95,18 @@ # define cpu_is_mx35() (0) #endif +#ifdef CONFIG_ARCH_SCMA11 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_SCMA11 +# endif +# define cpu_is_scma11() (mxc_cpu_type == MXC_CPU_SCMA11) +#else +# define cpu_is_scma11() (0) +#endif + #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10) #define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4) diff --git a/arch/arm/plat-mxc/include/mach/scma11.h b/arch/arm/plat-mxc/include/mach/scma11.h new file mode 100644 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/scma11.h @@ -0,0 +1,404 @@ +/* + * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. + * - Platform specific register memory map + * + * Copyright 2005-2007 Motorola, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Date Author Comment + * 10/2006 Motorola Added phys to virt address mappings for Motorola specific + * products. Also added additional ethernet, LCD and GPIO + * #defines as well as several WFN bug fixes. + * 01/2007 Motorola Added FIQ_START for watchdog debug support. + */ +#ifndef __ASM_ARM_ARCH_MXC91231_H_ +#define __ASM_ARM_ARCH_MXC91231_H_ + +#define MXC_TIMER_CLK 13000000 +#define MXC_TIMER_DIVIDER 1 + +/*! + * Register an interrupt handler for the SMN as well as the SCC. In some + * implementations, the SMN is not connected at all, and in others, it is + * on the same interrupt line as the SCM. Comment this line out accordingly + */ +#define USE_SMN_INTERRUPT + +/* + * This define specifies whether the muxed general purpose interrupt + * lines from MU is integrated with the ARM core + */ +#define MU_MUX_GN_INTS 1 + +/* + * UART Chip level Configuration that a user may not have to edit. These + * configuration vary depending on how the UART module is integrated with + * the ARM core + */ +#define MXC_UART_NR 3 +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive Irda data. + */ +#define MXC_UART_IR_RXDMUX 0x0004 + +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive UART data. + */ +#define MXC_UART_RXDMUX 0 + +/* + * L2CC + */ +#define L2CC_BASE_ADDR 0x30000000 +#define L2CC_BASE_ADDR_VIRT 0xF9000000 +#define L2CC_SIZE SZ_64K + +/* + * AIPS 1` + */ +#define AIPS1_BASE_ADDR 0x43F00000 +#define AIPS1_BASE_ADDR_VIRT 0xFC000000 +#define AIPS1_SIZE SZ_1M + +#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR +#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x04000) +#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x08000) +#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0C000) +#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x10000) +#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x14000) +#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x18000) +#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x80000) +#define MU_BASE_ADDR (AIPS1_BASE_ADDR + 0x88000) +#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x90000) +#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x94000) +#define DSM_BASE_ADDR (AIPS1_BASE_ADDR + 0x98000) +#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x9C000) +#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0xA0000) +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0xA8000) +#define IOMUX_AP_BASE_ADDR (AIPS1_BASE_ADDR + 0xAC000) +#define CTI_AP_BASE_ADDR (AIPS1_BASE_ADDR + 0xB8000) + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x53F00000 +#define AIPS2_BASE_ADDR_VIRT 0xFC100000 +#define AIPS2_SIZE SZ_1M + +#define GEMK_BASE_ADDR (AIPS2_BASE_ADDR + 0x8C000) +#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x90000) +#define EPIT1_AP_BASE_ADDR (AIPS2_BASE_ADDR + 0x94000) +#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0xAC000) +#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0xB0000) +#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0xC0000) +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0xC4000) +#define EDIO_BASE_ADDR (AIPS2_BASE_ADDR + 0xC8000) +#define GPIO1_AP_BASE_ADDR (AIPS2_BASE_ADDR + 0xCC000) +#define GPIO2_AP_BASE_ADDR (AIPS2_BASE_ADDR + 0xD0000) +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0xD4000) +#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0xD8000) +#define WDOG1_BASE_ADDR (AIPS2_BASE_ADDR + 0xDC000) +#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0xE0000) +#define GPIO3_AP_BASE_ADDR (AIPS2_BASE_ADDR + 0xE4000) +#define WDOG2_BASE_ADDR (AIPS2_BASE_ADDR + 0xE8000) +#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0xEC000) +#define LPMC_BASE_ADDR (AIPS2_BASE_ADDR + 0xF0000) + +/* + * SPBA global module enabled #0 + */ +#define SPBA0_BASE_ADDR 0x50000000 +#define SPBA0_BASE_ADDR_VIRT 0xFC200000 +#define SPBA0_SIZE SZ_1M + +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x04000) +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x08000) +#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0C000) +#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x10000) +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x14000) +#define SIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x18000) +#define SIM1_BASE_ADDR SIM_BASE_ADDR +#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x1C000) +#define CTI_SDMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x20000) +#define USBOTG_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x24000) +#define USBOTG_DATA_BASE_ADDR (SPBA0_BASE_ADDR + 0x28000) +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x30000) +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x3C000) +#define IOMUX_COM_BASE_ADDR (SPBA0_BASE_ADDR + 0x40000) +#define CRM_COM_BASE_ADDR (SPBA0_BASE_ADDR + 0x44000) +#define CRM_AP_BASE_ADDR (SPBA0_BASE_ADDR + 0x48000) +#define PLL0_BASE_ADDR (SPBA0_BASE_ADDR + 0x4C000) +#define PLL1_BASE_ADDR (SPBA0_BASE_ADDR + 0x50000) +#define PLL2_BASE_ADDR (SPBA0_BASE_ADDR + 0x54000) +#define GPIO4_SH_BASE_ADDR (SPBA0_BASE_ADDR + 0x58000) +#define HAC_BASE_ADDR (SPBA0_BASE_ADDR + 0x5C000) +#define SAHARA_BASE_ADDR (SPBA0_BASE_ADDR + 0x5C000) +#define PLL3_BASE_ADDR (SPBA0_BASE_ADDR + 0x60000) + +/* + * SPBA global module enabled #1 + */ +#define SPBA1_BASE_ADDR 0x52000000 +#define SPBA1_BASE_ADDR_VIRT 0xFC300000 +#define SPBA1_SIZE SZ_1M + +#define MQSPI_BASE_ADDR (SPBA1_BASE_ADDR + 0x34000) +#define EL1T_BASE_ADDR (SPBA1_BASE_ADDR + 0x38000) + +/*! + * Defines for SPBA modules + */ +#define SPBA_SDHC1 0x04 +#define SPBA_SDHC2 0x08 +#define SPBA_UART3 0x0C +#define SPBA_CSPI2 0x10 +#define SPBA_SSI2 0x14 +#define SPBA_SIM 0x18 +#define SPBA_IIM 0x1C +#define SPBA_CTI_SDMA 0x20 +#define SPBA_USBOTG_CTRL_REGS 0x24 +#define SPBA_USBOTG_DATA_REGS 0x28 +#define SPBA_CSPI1 0x30 +#define SPBA_MQSPI 0x34 +#define SPBA_EL1T 0x38 +#define SPBA_IOMUX 0x40 +#define SPBA_CRM_COM 0x44 +#define SPBA_CRM_AP 0x48 +#define SPBA_PLL0 0x4C +#define SPBA_PLL1 0x50 +#define SPBA_PLL2 0x54 +#define SPBA_GPIO4 0x58 +#define SPBA_SAHARA 0x5C + +/* + * ROMP and AVIC + */ +#define ROMP_BASE_ADDR 0x60000000 +#define ROMP_BASE_ADDR_VIRT 0xFC400000 +#define ROMP_SIZE SZ_64K + +#define AVIC_BASE_ADDR 0x68000000 +#define AVIC_BASE_ADDR_VIRT 0xFC410000 +#define AVIC_SIZE SZ_64K + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define X_MEMC_BASE_ADDR 0xB8000000 +#define X_MEMC_BASE_ADDR_VIRT 0xFC420000 +#define X_MEMC_SIZE SZ_64K + +#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) +#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) +#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) +#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) +#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) + +/* + * Memory regions and CS + * CPLD is connected on CS4 + * CS5 is TP1021 or it is not connected + * */ +#define FB_RAM_BASE_ADDR 0x78000000 +#define FB_RAM_SIZE SZ_256K +#define CSD0_BASE_ADDR 0x80000000 +#define CSD1_BASE_ADDR 0x90000000 +#define CS0_BASE_ADDR 0xA0000000 +#define CS1_BASE_ADDR 0xA8000000 +#define CS2_BASE_ADDR 0xB0000000 +#define CS3_BASE_ADDR 0xB2000000 + +#define CS4_BASE_ADDR 0xB4000000 +#define CS4_SIZE SZ_16M + +#define CS5_BASE_ADDR 0xB6000000 +#define CS5_SIZE SZ_16M + +/*! + * This macro defines the physical to virtual address mapping for all the + * peripheral modules. It is used by passing in the physical address as x + * and returning the virtual address. If the physical address is not mapped, + * it returns 0xDEADBEEF + * Add new elif's for any new boards based off scma11 platform + */ +#define IO_ADDRESS(x) \ + (void __iomem *) \ + (((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\ + ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ + ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ + ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ + ((x >= SPBA1_BASE_ADDR) && (x < (SPBA1_BASE_ADDR + SPBA1_SIZE))) ? SPBA1_IO_ADDRESS(x):\ + ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ + ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ + ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ + 0xDEADBEEF) +/* + * define the address mapping macros: in physical address order + */ + +#define L2CC_IO_ADDRESS(x) \ + (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) + +#define AIPS1_IO_ADDRESS(x) \ + (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) + +#define SPBA0_IO_ADDRESS(x) \ + (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) + +#define SPBA1_IO_ADDRESS(x) \ + (((x) - SPBA1_BASE_ADDR) + SPBA1_BASE_ADDR_VIRT) + +#define AIPS2_IO_ADDRESS(x) \ + (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) + +#define ROMP_IO_ADDRESS(x) \ + (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) + +#define AVIC_IO_ADDRESS(x) \ + (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) + +#define X_MEMC_IO_ADDRESS(x) \ + (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) + +/* + * DMA request assignments + */ +#define DMA_REQ_reserved31 31 +#define DMA_REQ_NFC 30 +#define DMA_REQ_SSI1_TX1 29 +#define DMA_REQ_SSI1_RX1 28 +#define DMA_REQ_SSI1_TX2 27 +#define DMA_REQ_SSI1_RX2 26 +#define DMA_REQ_SSI2_TX1 25 +#define DMA_REQ_SSI2_RX1 24 +#define DMA_REQ_SSI2_TX2 23 +#define DMA_REQ_SSI2_RX2 22 +#define DMA_REQ_SDHC2 21 +#define DMA_REQ_SDHC1 20 +#define DMA_REQ_UART1_TX 19 +#define DMA_REQ_UART1_RX 18 +#define DMA_REQ_UART2_TX 17 +#define DMA_REQ_UART2_RX 16 +#define DMA_REQ_UART3_TX 15 +#define DMA_REQ_UART3_RX 14 +#define DMA_REQ_EXT13 13 +#define DMA_REQ_EXT12 12 +#define DMA_REQ_reserved11 11 +#define DMA_REQ_reserved10 10 +#define DMA_REQ_CSPI1_TX 9 +#define DMA_REQ_CSPI1_RX 8 +#define DMA_REQ_CSPI2_TX 7 +#define DMA_REQ_CSPI2_RX 6 +#define DMA_REQ_reserved5 5 +#define DMA_REQ_reserved4 4 +#define DMA_REQ_reserved3 3 +#define DMA_REQ_reserved2 2 +#define DMA_REQ_reserved1 1 +#define DMA_REQ_reserved0 0 + +/* + * Interrupt numbers + * + * TODO: Interrupt numbers for first virtio release. + * To be finalized once board schematic/Virtio ready. + */ +#define MXC_INT_BASE 0 +#define MXC_INT_GPIO3 0 +#define MXC_INT_EL1T_CI 1 +#define MXC_INT_EL1T_RFCI 2 +#define MXC_INT_EL1T_RFI 3 +#define MXC_INT_EL1T_MCU 4 +#define MXC_INT_EL1T_IPI 5 +#define MXC_INT_MU_GEN 6 +#define MXC_INT_GPIO4 7 +#define MXC_INT_MMC_SDHC2 8 +#define MXC_INT_MMC_SDHC1 9 +#define MXC_INT_I2C 10 +#define MXC_INT_SSI2 11 +#define MXC_INT_SSI1 12 +#define MXC_INT_CSPI2 13 +#define MXC_INT_CSPI1 14 +#define MXC_INT_RTIC 15 +#define MXC_INT_SAHARA 15 +#define MXC_INT_HAC 15 +#define MXC_INT_UART3_RX 16 +#define MXC_INT_UART3_TX 17 +#define MXC_INT_UART3_MINT 18 +#define MXC_INT_ECT 19 +#define MXC_INT_SIM_IPB 20 +#define MXC_INT_SIM_DATA 21 +#define MXC_INT_RNGA 22 +#define MXC_INT_DSM_AP 23 +#define MXC_INT_KPP 24 +#define MXC_INT_RTC 25 +#define MXC_INT_PWM 26 +#define MXC_INT_GEMK_AP 27 +#define MXC_INT_EPIT 28 +#define MXC_INT_GPT 29 +#define MXC_INT_UART2_RX 30 +#define MXC_INT_UART2_TX 31 +#define MXC_INT_UART2_MINT 32 +#define MXC_INT_NANDFC 33 +#define MXC_INT_SDMA 34 +#define MXC_INT_USB_WAKEUP 35 +#define MXC_INT_USB_SOF 36 +#define MXC_INT_PMU_EVTMON 37 +#define MXC_INT_USB_FUNC 38 +#define MXC_INT_USB_DMA 39 +#define MXC_INT_USB_CTRL 40 +#define MXC_INT_IPU_ERR 41 +#define MXC_INT_IPU_SYN 42 +#define MXC_INT_UART1_RX 43 +#define MXC_INT_UART1_TX 44 +#define MXC_INT_UART1_MINT 45 +#define MXC_INT_IIM 46 +#define MXC_INT_MU_RX_OR 47 +#define MXC_INT_MU_TX_OR 48 +#define MXC_INT_SCC_SCM 49 +#define MXC_INT_SCC_SMN 50 +#define MXC_INT_GPIO2 51 +#define MXC_INT_GPIO1 52 +#define MXC_INT_MQSPI1 53 +#define MXC_INT_MQSPI2 54 +#define MXC_INT_WDOG2 55 +#define MXC_INT_EXT_INT7 56 +#define MXC_INT_EXT_INT6 57 +#define MXC_INT_EXT_INT5 58 +#define MXC_INT_EXT_INT4 59 +#define MXC_INT_EXT_INT3 60 +#define MXC_INT_EXT_INT2 61 +#define MXC_INT_EXT_INT1 62 +#define MXC_INT_EXT_INT0 63 + +#define MXC_MAX_INT_LINES 63 +#define MXC_MAX_EXT_LINES 8 + +#define GPIO_DR 0x00 +#define GPIO_GDIR 0x04 +#define GPIO_PSR 0x08 +#define GPIO_ICR1 0x0c +#define GPIO_ICR2 0x10 +#define GPIO_IMR 0x14 +#define GPIO_ISR 0x18 +#define GPIO_INT_LOW_LEV 0x0 +#define GPIO_INT_HIGH_LEV 0x1 +#define GPIO_INT_RISE_EDGE 0x2 +#define GPIO_INT_FALL_EDGE 0x3 +#define GPIO_INT_NONE 0x4 + +#endif /* __ASM_ARM_ARCH_MXC91231_H_ */ diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -21,10 +21,26 @@ #ifndef __ASM_ARCH_MXC_SYSTEM_H__ #define __ASM_ARCH_MXC_SYSTEM_H__ +#ifndef CONFIG_ARCH_SCMA11 static inline void arch_idle(void) { cpu_do_idle(); } +#else +#include +#include +static inline void arch_idle(void) +{ + unsigned long crm_ctl; + + /* When cpu_idle()'ing, go to WAIT mode */ + crm_ctl = __raw_readl(IO_ADDRESS(DSM_BASE_ADDR+0x50)); + crm_ctl &= ~0x3; + crm_ctl |= 0x1; + __raw_writel(crm_ctl, IO_ADDRESS(DSM_BASE_ADDR+0x50)); + cpu_do_idle(); +} +#endif void arch_reset(char mode, const char *cmd); diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -26,6 +26,8 @@ #define CLOCK_TICK_RATE 13300000 #elif defined CONFIG_ARCH_MX3 #define CLOCK_TICK_RATE 16625000 +#elif defined CONFIG_ARCH_SCMA11 +#define CLOCK_TICK_RATE 13000000 #endif #endif /* __ASM_ARCH_MXC_TIMEX_H__ */ diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -41,6 +41,7 @@ /* * Reset the system. It is called by machine_restart(). */ +#ifndef CONFIG_ARCH_SCMA11 void arch_reset(char mode, const char *cmd) { if (!cpu_is_mx1()) { @@ -65,3 +66,4 @@ /* we'll take a jump through zero as a poor second */ cpu_reset(0); } +#endif /* CONFIG_ARCH_SCMA11 */ diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -47,7 +47,7 @@ #define MX2_TSTAT_CAPT (1 << 1) #define MX2_TSTAT_COMP (1 << 0) -/* MX31, MX35 */ +/* MX31, MX35, SCMA11 */ #define MX3_TCTL_WAITEN (1 << 3) #define MX3_TCTL_CLK_IPG (1 << 6) #define MX3_TCTL_FRR (1 << 9) @@ -66,7 +66,7 @@ { unsigned int tmp; - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_scma11()) __raw_writel(0, timer_base + MX3_IR); else { tmp = __raw_readl(timer_base + MXC_TCTL); @@ -76,7 +76,7 @@ static inline void gpt_irq_enable(void) { - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_scma11()) __raw_writel(1<<0, timer_base + MX3_IR); else { __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, @@ -90,7 +90,7 @@ __raw_writel(0, timer_base + MX1_2_TSTAT); if (cpu_is_mx2()) __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_scma11()) __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); } @@ -117,7 +117,7 @@ { unsigned int c = clk_get_rate(timer_clk); - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_scma11()) clocksource_mxc.read = mx3_get_cycles; clocksource_mxc.mult = clocksource_hz2mult(c, @@ -180,7 +180,7 @@ if (mode != clockevent_mode) { /* Set event time into far-far future */ - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_scma11()) __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, timer_base + MX3_TCMP); else @@ -233,7 +233,7 @@ struct clock_event_device *evt = &clockevent_mxc; uint32_t tstat; - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_scma11()) tstat = __raw_readl(timer_base + MX3_TSTAT); else tstat = __raw_readl(timer_base + MX1_2_TSTAT); @@ -264,7 +264,7 @@ { unsigned int c = clk_get_rate(timer_clk); - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_scma11()) clockevent_mxc.set_next_event = mx3_set_next_event; clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, @@ -298,8 +298,8 @@ timer_base = IO_ADDRESS(GPT1_BASE_ADDR); irq = MXC_INT_GPT1; #endif - } else if (cpu_is_mx3()) { -#ifdef CONFIG_ARCH_MX3 + } else if (cpu_is_mx3() || cpu_is_scma11()) { +#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_SCMA11 timer_base = IO_ADDRESS(GPT1_BASE_ADDR); irq = MXC_INT_GPT; #endif @@ -313,7 +313,7 @@ __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_scma11()) tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;