# HG changeset patch
# User Dmitriy Taychenachev <dimichxp@gmail.com>
# Date 1247714660 -32400

diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -67,7 +67,7 @@
 #define UBIR  0xa4 /* BRM Incremental Register */
 #define UBMR  0xa8 /* BRM Modulator Register */
 #define UBRC  0xac /* Baud Rate Count Register */
-#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
+#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_SCMA11
 #define ONEMS 0xb0 /* One Millisecond register */
 #define UTS   0xb4 /* UART Test Register */
 #endif
@@ -104,7 +104,7 @@
 #ifdef CONFIG_ARCH_MX1
 #define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */
 #endif
-#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
+#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_SCMA11
 #define  UCR1_UARTCLKEN  (0)	 /* not present on mx2/mx3 */
 #endif
 #define  UCR1_DOZE       (1<<1)	 /* Doze */
@@ -128,7 +128,9 @@
 #define  UCR3_DSR        (1<<10) /* Data set ready */
 #define  UCR3_DCD        (1<<9)  /* Data carrier detect */
 #define  UCR3_RI         (1<<8)  /* Ring indicator */
+#if !defined(CONFIG_ARCH_SCMA11)
 #define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */
+#endif
 #define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
 #define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 #define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
@@ -136,16 +138,20 @@
 #define  UCR3_REF25 	 (1<<3)  /* Ref freq 25 MHz, only on mx1 */
 #define  UCR3_REF30 	 (1<<2)  /* Ref Freq 30 MHz, only on mx1 */
 #endif
-#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
+#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_SCMA11
 #define  UCR3_RXDMUXSEL	 (1<<2)  /* RXD Muxed Input Select, on mx2/mx3 */
 #endif
 #define  UCR3_INVT  	 (1<<1)  /* Inverted Infrared transmission */
+#if !defined(CONFIG_ARCH_SCMA11)
 #define  UCR3_BPEN  	 (1<<0)  /* Preset registers enable */
+#endif
 #define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
 #define  UCR4_INVR  	 (1<<9)  /* Inverted infrared reception */
 #define  UCR4_ENIRI 	 (1<<8)  /* Serial infrared interrupt enable */
 #define  UCR4_WKEN  	 (1<<7)  /* Wake interrupt enable */
+#if !defined(CONFIG_ARCH_SCMA11)
 #define  UCR4_REF16 	 (1<<6)  /* Ref freq 16 MHz */
+#endif
 #define  UCR4_IRSC  	 (1<<5)  /* IR special case */
 #define  UCR4_TCEN  	 (1<<3)  /* Transmit complete interrupt enable */
 #define  UCR4_BKEN  	 (1<<2)  /* Break condition interrupt enable */