# HG changeset patch
# User Dmitriy Taychenachev <dimichxp@gmail.com>
# Date 1247714825 -32400

diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -44,7 +44,8 @@
 #define SPI_RXDATA		(0x00)
 #define SPI_TXDATA		(0x04)
 #define SPI_CONTROL		(0x08)
-#define SPI_INT_STATUS		(0x0C)
+#define SPI_INT			(0x0C)
+#define SPI_STAT		(0x0C)
 #define SPI_TEST		(0x10)
 #define SPI_PERIOD		(0x14)
 #define SPI_DMA			(0x18)
@@ -309,7 +310,7 @@
 		chip->control);
 	writel(chip->test, regs + SPI_TEST);
 	writel(chip->period, regs + SPI_PERIOD);
-	writel(0, regs + SPI_INT_STATUS);
+	writel(0, regs + SPI_INT);
 	writel(chip->control, regs + SPI_CONTROL);
 }
 
@@ -576,7 +577,7 @@
 
 	/* Bring SPI to sleep; restore_state() and pump_transfer()
 	   will do new setup */
-	writel(0, regs + SPI_INT_STATUS);
+	writel(0, regs + SPI_INT);
 	writel(0, regs + SPI_DMA);
 
 	/* Unconditioned deselct */
@@ -619,20 +620,20 @@
 	imx_dma_disable(channel);
 
 	/* Now waits for TX FIFO empty */
-	writel(SPI_INTEN_TE, drv_data->regs + SPI_INT_STATUS);
+	writel(SPI_INTEN_TE, drv_data->regs + SPI_INT);
 }
 
 static irqreturn_t dma_transfer(struct driver_data *drv_data)
 {
-	u32 status;
+	u32 status, intctl;
 	struct spi_message *msg = drv_data->cur_msg;
 	void __iomem *regs = drv_data->regs;
 
-	status = readl(regs + SPI_INT_STATUS);
+	status = readl(regs + SPI_STAT);
+	intctl = readl(regs + SPI_INT);
 
-	if ((status & (SPI_INTEN_RO | SPI_STATUS_RO))
-			== (SPI_INTEN_RO | SPI_STATUS_RO)) {
-		writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
+	if ((intctl & SPI_INTEN_RO) && (status & SPI_STATUS_RO)) {
+		writel(intctl & ~SPI_INTEN, regs + SPI_INT);
 
 		imx_dma_disable(drv_data->tx_channel);
 		imx_dma_disable(drv_data->rx_channel);
@@ -650,7 +651,7 @@
 	}
 
 	if (status & SPI_STATUS_TE) {
-		writel(status & ~SPI_INTEN_TE, regs + SPI_INT_STATUS);
+		writel(intctl & ~SPI_INTEN_TE, regs + SPI_INT);
 
 		if (drv_data->rx) {
 			/* Wait end of transfer before read trailing data */
@@ -701,14 +702,15 @@
 {
 	struct spi_message *msg = drv_data->cur_msg;
 	void __iomem *regs = drv_data->regs;
-	u32 status;
+	u32 status, intctl;
 	irqreturn_t handled = IRQ_NONE;
 
-	status = readl(regs + SPI_INT_STATUS);
+	status = readl(regs + SPI_STAT);
+	intctl = readl(regs + SPI_INT);
 
-	if (status & SPI_INTEN_TE) {
+	if (intctl & SPI_INTEN_TE) {
 		/* TXFIFO Empty Interrupt on the last transfered word */
-		writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
+		writel(intctl & ~SPI_INTEN, regs + SPI_INT);
 		dev_dbg(&drv_data->pdev->dev,
 			"interrupt_wronly_transfer - end of tx\n");
 
@@ -734,11 +736,11 @@
 			if (write(drv_data)) {
 				/* End of TXFIFO writes,
 				   now wait until TXFIFO is empty */
-				writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
+				writel(SPI_INTEN_TE, regs + SPI_INT);
 				return IRQ_HANDLED;
 			}
 
-			status = readl(regs + SPI_INT_STATUS);
+			status = readl(regs + SPI_STAT);
 
 			/* We did something */
 			handled = IRQ_HANDLED;
@@ -752,15 +754,16 @@
 {
 	struct spi_message *msg = drv_data->cur_msg;
 	void __iomem *regs = drv_data->regs;
-	u32 status, control;
+	u32 status, intctl, control;
 	irqreturn_t handled = IRQ_NONE;
 	unsigned long limit;
 
-	status = readl(regs + SPI_INT_STATUS);
+	status = readl(regs + SPI_STAT);
+	intctl = readl(regs + SPI_INT);
 
-	if (status & SPI_INTEN_TE) {
+	if (intctl & SPI_INTEN_TE) {
 		/* TXFIFO Empty Interrupt on the last transfered word */
-		writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
+		writel(intctl & ~SPI_INTEN, regs + SPI_INT);
 		dev_dbg(&drv_data->pdev->dev,
 			"interrupt_transfer - end of tx\n");
 
@@ -811,7 +814,7 @@
 			if (status & SPI_STATUS_RO) {
 				/* RXFIFO overrun, abort message end wait
 				   until TXFIFO is empty */
-				writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
+				writel(SPI_INTEN_TE, regs + SPI_INT);
 
 				dev_warn(&drv_data->pdev->dev,
 					"interrupt_transfer - fifo overun\n"
@@ -830,11 +833,11 @@
 			if (write(drv_data)) {
 				/* End of TXFIFO writes,
 				   now wait until TXFIFO is empty */
-				writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
+				writel(SPI_INTEN_TE, regs + SPI_INT);
 				return IRQ_HANDLED;
 			}
 
-			status = readl(regs + SPI_INT_STATUS);
+			status = readl(regs + SPI_STAT);
 
 			/* We did something */
 			handled = IRQ_HANDLED;
@@ -1025,7 +1028,7 @@
 			imx_dma_enable(drv_data->rx_channel);
 
 			/* Enable SPI interrupt */
-			writel(SPI_INTEN_RO, regs + SPI_INT_STATUS);
+			writel(SPI_INTEN_RO, regs + SPI_INT);
 
 			/* Set SPI to request DMA service on both
 			   Rx and Tx half fifo watermark */
@@ -1055,9 +1058,9 @@
 		/* Enable SPI interrupt */
 		if (drv_data->rx)
 			writel(SPI_INTEN_TH | SPI_INTEN_RO,
-				regs + SPI_INT_STATUS);
+				regs + SPI_INT);
 		else
-			writel(SPI_INTEN_TH, regs + SPI_INT_STATUS);
+			writel(SPI_INTEN_TH, regs + SPI_INT);
 	}
 }