# HG changeset patch
# User Dmitriy Taychenachev <dimichxp@gmail.com>
# Date 1248616040 -32400

diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -73,6 +73,7 @@
 
 #define SPI_CONTROL_BITCOUNT_MASK	(0xF)		/* Bit Count Mask */
 #define SPI_CONTROL_BITCOUNT(n)		(((n) - 1) & SPI_CONTROL_BITCOUNT_MASK)
+#define SPI_BITCOUNT_MAX		(16)		/* Max 16 bits per word */
 #define SPI_CONTROL_POL			(0x1 << 4)      /* Clock Polarity Mask */
 #define SPI_CONTROL_POL_ACT_HIGH	(0x0 << 4)      /* Active high pol. (0=idle) */
 #define SPI_CONTROL_POL_ACT_LOW		(0x1 << 4)      /* Active low pol. (1=idle) */
@@ -163,6 +164,7 @@
 #define SPI_CONTROL_DATARATE_BAD	(SPI_CONTROL_DATARATE_MIN + 1)
 #define SPI_CONTROL_BITCOUNT_MASK	(0x1F << 20)	/* Bit Count Mask */
 #define SPI_CONTROL_BITCOUNT(n)		(((n) - 1) << 20 & SPI_CONTROL_BITCOUNT_MASK)
+#define SPI_BITCOUNT_MAX		(32)		/* Max 32 bits per word */
 
 /* SPI Interrupt/Status Register Bit Fields & Masks */
 #define SPI_STATUS_TE	(0x1 << 0)	/* TXFIFO Empty Status */
@@ -284,6 +286,8 @@
 */
 #define u32_EDIT(r, m, v)		r = (r & ~(m)) | (v)
 
+#define N_BYTES(bits)			(((bits)<=16) ? (bits)/8 : 4)
+
 /* Message state */
 #define START_STATE			((void*)0)
 #define RUNNING_STATE			((void*)1)
@@ -447,7 +451,7 @@
 	u32 remaining_writes;
 	u32 fifo_avail_space;
 	u32 n;
-	u16 d;
+	u32 d;
 
 	/* Compute how many fifo writes to do */
 	remaining_writes = (u32)(tx_end - tx) / n_bytes;
@@ -459,11 +463,11 @@
 	n = min(remaining_writes, fifo_avail_space);
 
 	dev_dbg(&drv_data->pdev->dev,
-		"write type %s\n"
+		"write type u%d\n"
 		"    remaining writes = %d\n"
 		"    fifo avail space = %d\n"
 		"    fifo writes      = %d\n",
-		(n_bytes == 1) ? "u8" : "u16",
+		n_bytes*8,
 		remaining_writes,
 		fifo_avail_space,
 		n);
@@ -481,12 +485,18 @@
 					writel(d, regs + SPI_TXDATA);
 					tx += 1;
 				}
-			} else {
+			} else if (n_bytes == 2) {
 				while (n--) {
 					d = *(u16*)tx;
 					writel(d, regs + SPI_TXDATA);
 					tx += 2;
 				}
+			} else {
+				while (n--) {
+					d = *(u32*)tx;
+					writel(d, regs + SPI_TXDATA);
+					tx += 4;
+				}
 			}
 		}
 
@@ -510,7 +520,7 @@
 	u32 remaining_reads;
 	u32 fifo_rxcnt;
 	u32 n;
-	u16 d;
+	u32 d;
 
 	/* Compute how many fifo reads to do */
 	remaining_reads = (u32)(rx_end - rx) / n_bytes;
@@ -519,11 +529,11 @@
 	n = min(remaining_reads, fifo_rxcnt);
 
 	dev_dbg(&drv_data->pdev->dev,
-		"read type %s\n"
+		"read type u%d\n"
 		"    remaining reads = %d\n"
 		"    fifo rx count   = %d\n"
 		"    fifo reads      = %d\n",
-		(n_bytes == 1) ? "u8" : "u16",
+		n_bytes*8,
 		remaining_reads,
 		fifo_rxcnt,
 		n);
@@ -536,12 +546,18 @@
 				*((u8*)rx) = d;
 				rx += 1;
 			}
-		} else {
+		} else if (n_bytes == 2){
 			while (n--) {
 				d = readl(regs + SPI_RXDATA);
 				*((u16*)rx) = d;
 				rx += 2;
 			}
+		} else {
+			while (n--) {
+				d = readl(regs + SPI_RXDATA);
+				*((u32*)rx) = d;
+				rx += 4;
+			}
 		}
 
 		/* Update rx pointer */
@@ -1063,7 +1079,7 @@
 		drv_data->n_bytes = chip->n_bytes;
 	} else
 		/* Use per-transfer setup */
-		drv_data->n_bytes = (tmp <= 8) ? 1 : 2;
+		drv_data->n_bytes = N_BYTES(tmp);
 	u32_EDIT(control, SPI_CONTROL_BITCOUNT_MASK,
 		   SPI_CONTROL_BITCOUNT(tmp));
 
@@ -1240,7 +1256,7 @@
 	max_speed_hz = spi->max_speed_hz;
 	list_for_each_entry(trans, &msg->transfers, transfer_list) {
 		tmp = trans->bits_per_word;
-		if (tmp > 16) {
+		if (tmp > SPI_BITCOUNT_MAX) {
 			dev_err(&drv_data->pdev->dev,
 				"message rejected : "
 				"invalid transfer bits_per_word (%d bits)\n",
@@ -1401,7 +1417,7 @@
 
 	/* SPI word width */
 	tmp = spi->bits_per_word;
-	if (tmp > 16) {
+	if (tmp > SPI_BITCOUNT_MAX) {
 		status = -EINVAL;
 		dev_err(&spi->dev,
 			"setup - "
@@ -1418,7 +1434,7 @@
 	chip->bits_per_word = tmp;
 	u32_EDIT(chip->control, SPI_CONTROL_BITCOUNT_MASK,
 		   SPI_CONTROL_BITCOUNT(tmp));
-	chip->n_bytes = (tmp <= 8) ? 1 : 2;
+	chip->n_bytes = N_BYTES(tmp);
 
 	/* SPI datarate */
 	tmp = spi_data_rate(drv_data, spi->max_speed_hz);